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Xilinx Answer #8531 : ModelSim XE (MXE) : starting the vsim GUI I get a window titled Error in Startup Script
Xilinx Answer #8079 : MODELSIM XE (MTI): How is the performance affected by the number of lines in the HDL source file?
Xilinx Answer #8066 : MODELSIM VLOG (MTI): How to compile the XilinxCoreLib (COREGEN) Verilog library?
Xilinx Answer #7915 : MODELSIM-XE (MTI): How do to obtain it? When is it available?
Xilinx Answer #7804 : MODELSIM (MTI): How to save waveform results?
Xilinx Answer #6540 : MODELSIM VLOG: ERROR: ../../../<logiblox_module.v>: Instantiation of 'X_OR' failed (design unit not found)
Xilinx Answer #6538 : MODELSIM VLOG: Error: Unresolved reference to 'glbl' when trying to simulate a Verilog design with Alliance 2.1 (or later)
Xilinx Answer #6300 : V2.1i COREGEN, MTI: "Error: Unknown identifier 'xilinxcorelib"'"when compiling Coregen VHDL Baseblox in MTI
Xilinx Answer #5255 : SIMPRIMS: What does it mean when I get setup or hold time violations in my simulation? What do I do?
Xilinx Answer #4413 : ModelSim: ERROR (line number): Subprogram is ambiguous use -explicit option to disable
Xilinx Answer #4049 : MTI: Functional simulation with STARTBUF not connected properly may cause errors
Xilinx Answer #3767 : A1.4 and Modelsim: How to use the OSC4 component with VHDL simulation (Functional and Timing)
Xilinx Answer #2561 : MODELSIM (MTI): How to compile the 2.1 Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Xilinx Answer #1923 : MODELSIM: How to compile the 1.5 Simprim, LogiBLOX, Unisim, and Coregen HDL libraries?
Xilinx Answer #1548 : M1 V-System: VHDL/VITAL RAMs do not simulate properly or respond to stimuli on HP-UX
Xilinx Answer #1078 : MODELSIM VLOG (MTI): Running Verilog simulation
Xilinx Answer #889 : MODELSIM VLOG (MTI): WARNING: [TSCALE] - Module '...' does not have a `timescale directive in effect, but previous modules do