Answers Database UNISIMS: GSR/GTS behavior does not simulate with STARTUP_VIRTEX Verilog model. Record #2476 Product Family: Software Product Line: FPGA Implementation Product Part: Unisim Product Version: n/a Problem Title: UNISIMS: GSR/GTS behavior does not simulate with STARTUP_VIRTEX Verilog model. Problem Description: Urgency: Standard General Description: GSR/GTS behavior does not simulate with the STARTUP_VIRTEX UNISIM Verilog model. Solution 1: The UNISIM Verilog model for STARTUP_VIRTEX does not assign glbl.GSR and glbl.GTS to GSR and GTS, respectively. The behavioral models are using the GSR_SIGNAL methodology. To resolve this issue, the user can apply both methodologies for initializing GSR/GTS. Please see (Xilinx Solution 6537) regarding the usage of the glbl module in the Xilinx Alliance 2.1 (or greater) software. Please see (Xilinx Solution 3914) on the usage of the GSR_SIGNAL text macro. Please see (Xilinx Solution 5009) on how to drive the GSR pin. This is fixed in Service Pack 2 for Alliance 2.1i. End of Record #2476 - Last Modified: 10/21/99 10:45

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