Answers Database
CONCEPT-HDL: GSR/GTS behavior does not simulate with RAMB4* Verilog models.
Record #7331
Product Family: Software
Product Line: Cadence
Product Part: concept
Product Version: 1.7
Problem Title:
CONCEPT-HDL: GSR/GTS behavior does not simulate with RAMB4* Verilog models.
Problem Description:
Urgency: Standard
General Description:
The Concept-HDL behavioral models are not using the glbl.GSR methodology, but
the GSR_SIGNAL methodology. This will lead to bad simulation results when
toggling the GSR on a design with BlockRAM.
Please see (Xilinx Solution 6537) on the usage of the glbl module.
Please see (Xilinx Solution 3914) on the usage of the GSR_SIGNAL text macro.
Please see (Xilinx Solution 5009) on how to drive the GSR pin.
Solution 1:
The UNISIM Verilog models for RAMB4* does not assign glbl.GSR and
glbl.GTS to GSR and GTS, respectively. The behavioral models are
using the GSR_SIGNAL methodology.
To resolve this issue, the user can apply both methodologies for
initializing GSR/GTS.
Please see (Xilinx Solution 6537) regarding the usage of the glbl module
in the Xilinx Alliance 2.1 (or greater) software.
Please see (Xilinx Solution 3914) on the usage of the GSR_SIGNAL
text macro.
Please see (Xilinx Solution 5009) on how to drive the GSR pin.
End of Record #7331 - Last Modified: 10/22/99 14:32 |
