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Xilinx Answer #6893 : NGDAnno: What's GSUH
Xilinx Answer #5851 : 1.5i SP2 Virtex back annotation - Ngdanno issues warning stating that 100% back annotation is not possible.
Xilinx Answer #5545 : 1.5i Back Annotation - Ngdanno creates a dangling net in a design.
Xilinx Answer #5536 : 1.5i Ngdanno - ERROR:baspp - this design contains logic for which correlated back annotation ...
Xilinx Answer #5525 : 1.5i Virtex Back Annotation - Ngdanno does not back annotate delays on logical CLKDLL
Xilinx Answer #5520 : 1.5i Virtex Back Annotation - Ngdanno issues warning stating that 100% back annotation is not possible
Xilinx Answer #5158 : NGDANNO 1.5: FATAL_ERROR:basut:basutblist.c:348:1.2-Maximum iterator count exceeded
Xilinx Answer #4861 : 1.5i Ngdanno - Timing simulation for ROMs is overly conservative
Xilinx Answer #4506 : M1.5i/2.1i: Timing Report: Minimum Delay Reporting "-s min" for Timing Analyzer, TRCE, and NGDANNO
Xilinx Answer #3815 : A1.4/F1.4 Ngdanno - INTERNAL_ERROR:basnb:basnbconv.c:546:1.21
Xilinx Answer #3577 : 3100 F1.4/A1.4: NGDANNO: FATAL_ERROR:basna:basnasite.c:131.1.3 - cannot find BEL delay TCKI...
Xilinx Answer #3460 : M1.4 NGDANNO - Ngdanno fails to properly annotate back to logical representation.
Xilinx Answer #3459 : M1.4 Ngdanno - Timing discrepency between Trce and back annotated timing for EQN logic.
Xilinx Answer #3455 : M1.4 Ngdanno - ERROR : Non numeric pin number 'P90' found.
Xilinx Answer #3158 : NGDANNO : Warning: basna: 22 - NGDANNO found physical components for which...
Xilinx Answer #2375 : NGDANNO uses the max value only when different drivers drive the same net
Xilinx Answer #1863 : Back-Annotation Timing Data May Contain Overly Conservative Values for the Setup Requirements of Some IOB Input Flip-Flops and Latches. Physical Post-layout Simulation Occurs When NGDAnno Is Ca lled Without a Reference to the NGM File.