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Xilinx Answer #7721 : 2.1i Ngdanno: Constants become hanging nets in back-annotated HDL file causing unknown states in timing simulation
Xilinx Answer #7700 : 2.1i ngdanno warning : ngdexpander : 5 - STARTUP symbol... can be ignored
Xilinx Answer #7336 : 2.1i Ngdanno - Back annotated delay has 3.7ns added to tristate signal on an IOB.
Xilinx Answer #7322 : 2.1i Ngdanno - Virtex single and dual port RAM give setup violations for Physical Sim only.
Xilinx Answer #6913 : 2.1i Ngdanno: INTERNAL_ERROR:Anno:Ax.c:2094:1.1.2.40.2.4 - Ax::fixConfusedPins() cannot handle this configuration
Xilinx Answer #6665 : 2.1i NGDAnno: NGDAnno leaves BlockRAM's inputs unconnected if they are driven by more than one power/ground or constant signals.
Xilinx Answer #4506 : M1.5i/2.1i: Timing Report: Minimum Delay Reporting "-s min" for Timing Analyzer, TRCE, and NGDANNO