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In order to understand CPLDs (Complex Programmable Logic
Device), it is important to understand SPLDs. An SPLD (Simple
Programmable Logic Device) is a lot of gates with
interconnects that can be programmed to form desired logic
functions. There are two basic types of SPLDs: the PLA and the
PAL. The PLA has both a programmable AND array and a
programmable OR array and looks like this:
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![PLA Diagram](CPLD_what_files/pla.gif) Signetics - Cline
- 1975
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The PAL has a programmable AND array with a fixed OR array
and looks like this:
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![PAL Diagram](CPLD_what_files/pal.gif) MMI - Birkner -
1978
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CPLDs are simply a joining of 2 or more SPLDs on a single
IC using an interconnect, making them look like this: |
![CPLD Block Diagram](CPLD_what_files/logicblock.gif) All CPLDs
utilize macrocells in their device architecture. These
macrocells allow for combinatorial or sequential logic, and
also have the added flexibility for true or complement, along
with varied feedback paths.
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