The Spartan™ series of FPGAs (Spartan-II, Spartan-XL, and Spartan families) provides an effective ASIC production solution for many gate array designs. Derived from the successful Xilinx XC4000 and Virtex architectures and supporting up to 200,000 system gates, the Spartan series combines low ASIC production pricing with ASIC features such as on-chip RAM, low power, high performance and a robust selection of silicon-verified cores. The Spartan series is the first FPGA that meets all of the key cost, feature and performance criteria to realistically replace mask gate arrays in production. The Spartan series simply provides FPGA flexibility at ASIC prices!

ASIC Features

• On-chip SelectRAM dual port synchronous memory, placed at any location
• High performance - 80 MHz to 200 MHz system speeds
• Extensive verified portfolio of cores with AllianceCORE and LogiCORE products
• Built-in IEEE 1149.1 Boundary Scan support
• Low-power design permits Spartan devices to use inexpensive plastic packages
• Comprehensive Verilog and VHDL software support featuring Xilinx partners

ASIC Pricing

Xilinx can offer ASIC production pricing because the Spartan series has substantially reduced the die size and manufacturing costs. Cost targets were realized by using an advanced fabrication process and streamlining the FPGA features. Spartan series die has been decreased to limits imposed by the I/O pads and, as a result, has reached die size parity with many gate arrays. The Spartan FPGA and a mask ASIC with the same number of pins are equivalent in both size and cost. Spartan FPGAs offer volume production prices as low as $2.49 for Spartan-XL devices (5,000 system gates) and less than $10.00 for 100,000 gate Spartan-II devices.

Major ASIC Vendors Exit the Gate Array Business

The mask ASIC is actually penalized when migrating to the advanced deep sub-micron technologies at 0.35 mm and beyond. The penalty occurs because the transistors in deep sub-micron devices have shrunk much faster than metal lines. The result is that interconnect delay now dominates gate delay. Minimizing interconnect delay requires adding metal mask layers to create more routing resources. Each photo mask for the 0.35-mm process costs the ASIC supplier from $12,000-$15,000, as well as extending the prototype fab time. Since most ASICs today are fabricated with four or five custom metal layers, a $60,000-$75,000 cost for photo masks for each different customer design easily results in more than $100,000 in Non-Recurring Engineering (NRE) charges to the customer! The Spartan FPGA does not incur the same cost penalties of ASICs because each photo mask is created only once over the lifetime of the programmable device and serves hundreds of different customers. A deep sub-micron gate array loses much of its value when NREs are increased to more than $100,000 and prototype time is extended. This is a primary reason that gate array vendors such as LSI Logic and Motorola have exited the gate array business to focus on the complex Standard Cell market.

Total Cost Management Program

Spartan FPGAs also apply an aggressive Total Cost Management Program to hold product costs low. For example, the Xilinx Spartan series has

1. Limited the number of family members
2. Supported a very focused offering of inexpensive plastic packages
3. Optimized the test flow to reduce back end costs

The graph below plots the Spartan series parts according to system gates and number of I/O. As indicated, Spartan FPGAs are most cost-competitive in the low-density/high I/O (lower right) segment. The graph may be used as a reliable indicator to determine where the Spartan FPGAs can be most competitive with the ASIC in mass production. In short, when the Spartan FPGAs have the same number of I/Os as the ASIC and meet the density needs of your design, the FPGA will clearly be a better choice. By choosing Spartan devices you receive the time-to-production and reprogrammability advantages of FPGAs at ASIC prices. For higher densities and I/O counts, consider the Xilinx Virtex series.

Immediate Production

A fast ramp to full production is a primary advantage of these ASIC Replacement FPGAs. Spartan series deliveries are off the shelf from the Xilinx factory or from the inventory of our distribution partners, while typical ASIC lead times run from 8-16 weeks. Immediate Spartan FPGA production enables fast stocking of your sales channels and the rapid penetration of your customer base. Spartan FPGAs help you avoid the delays resulting from the long ASIC lead times that may substantially decrease revenues and profits throughout the life of the product. A well-known McKinsey study found that a six month delay costs one third of the profits over the lifetime of the product.

No FPGA Conversions for Spartan Series Users

The ASIC prices of Spartan series devices eliminate the need for low-density FPGA conversions to mask gate arrays. The Spartan FPGA user speeds time-to-production, minimizes development/NRE costs, and avoids unnecessary re-design risks by foregoing an FPGA-to-ASIC redesign.

Turnaround time:

• FPGA to ASIC conversions take a minimum of four months to production. The typical breakdown is the following:
  • Conversion time - 3 weeks average
  • Prototype time - 3 weeks best case
  • ASIC full production lead time - 8-16 weeks
  • Total conversion time-to-production = 4 months or more!

Costs: NRE/conversion fees - ~$10,000-$30,000 Cost of your internal conversion engineering efforts - ~$20,000 Simulate and verify redesign Qualify prototypes Transfer into production

• Converting FPGA features such as on-chip RAM, scan, reset, etc.
• Netlist changes adding new buffers and new I/O drive capabilities
• Change of timing to new ASIC architecture
• Porting of FPGA cores - complex licensing issues moving to new platform

• Spartan FPGAs are intended for fast development and cost-effective production
• Advantages of the FPGA in mass production:
  • No conversion engineering effort
  • No NRE or conversion fees
  • Cost reduction path through future generations
  • Immediate volume production!

Converging HDL Design Methodologies

Historically, programmable logic development methodology has lagged the ASIC industry by at least five years. This gap began to narrow in the early 1990s with the adoption of VHDL by a few PLD designers for more complex designs. As FPGAs continued to grow in density beyond the 20,000 gate level, the schematic design approach began to falter. It became obvious that implementation of VHDL support, and later Verilog support, would be necessary for the programmable vendors to continue offering greater device density and to provide the ASIC designer with a familiar design environment.

ASIC and FPGA Converging Design Approach

Today, the design methodologies have converged to the extent both ASIC and Xilinx FPGA design flows support behavioral simulation, extensive use of cores, RTL synthesis, timing and functional simulation, static timing analysis, floorplanning, etc. Xilinx has added other widely used ASIC-like tools such as minimum delay timing reports, more comprehensive static timing, team approach modular design and much more.

Xilinx HDL Training for Programmable Logic

Xilinx FAEs are available to work with ASIC designers to ease the learning curve of programmable designs. In addition, Xilinx offers formal instruction in HDL design through Xilinx training courses.

Comparing ASIC and Spartan FPGA HDL Design Flows

Spartan Family Choices	Spartan-II	Spartan-XL	Spartan
	Gates plus System-Level Features	Lowest Cost, Low Power	5V Supply
Max System Gates	15,000 to 200,000	5,000 to 40,000
Logic Gates	6,000 to 100,000	2,000 to 13,000
Block RAM	16K to 56K bits	N/A
I/O Perf.	200 MHz + 4 DLLs	100 MHz	80 MHz
Max I/O	86 to 284	77 to 224	77 to 205
Supply Voltage	2.5V	3.3V	5V
I/O Standards	16	4	2

Spartan-II Family Product Overview
Spartan-XL Family Product Overview
Spartan Family Product Overview