The Virtex-E Extended Memory (Virtex-EM) FPGA family delivers unprecendented on-chip memory to address highly buffered designs such as 160 Gbps network switches and high definition video applications. Xilinx now offers the first FPGA with over 1 million bits of block RAM, and also the first FPGA available with copper interconnect. Virtex-EM extends the highly successful Virtex-E architecture by maintaining all system level features, including:

True Dual-Port Embedded Block Memory for Highest Memory Bandwidth

Whether used as FIFOs, caches for high-speed parallel searches, or buffers for ATM packets, memory requirements are growing much faster than logic gate requirements. Xilinx pioneered the use of embedded distributed memory in our successful XC4000 FPGA family, and extended that memory hierarchy with the addition of True Dual-Port™ block RAM in the Virtex family.

Both block RAM and distributed RAM can also be configured as Content Addressable Memory (CAM), often used for fast lookup requirements. The Virtex-EM family extends the total True-Dual Port block RAM available to 560 kb in the XCV405E and 1,120 kb in the XCV812E, capable of 250 MHz performance. Designers can also interface to most types of external memory, including 266 MHz Double Data Rate (DDR) and Quad Data Rate (QDR) SRAM.

Related Application Notes:

	Data-Width Conversion FIFOs using Virtex Block SelectRAM Memory
	170MHz Synchronous and Asynchronous FIFOs Using the Virtex Block SelectRAM+ Features
	An Overview of Multiple CAM Designs in Virtex Devices
	CAM in ATM applications
	Designing Flexible, Fast CAMs with Virtex Slices
	CAM in Block Select RAM

Powerful Platform for Network Switch Fabrics

The Virtex-EM family was designed to support high-speed gigabit network applications, particularly scalable, buffered crossbar switches. A buffered crossbar switch, the choice for high-performance switch fabrics, is organized as a matrix that connects N input ports to N output ports.

These switches are memory intensive. For example, a switch connecting 16 8-bit input ports to 16 8-bit output ports with 4 priority levels would require 16 x 16 x 4 = 1024 buffers. With 1,120 kb of True Dual Port™ block RAM on the XCV812E, a fully populated 16 x 16 buffered cross bar switch with 4 priority levels can be implemented with 128-byte high-speed True Dual-Port RAM buffers at each cross-point.

Related Application Note:

High-Speed Buffered Crossbar Switch Design using Virtex-EM Devices

Technology to Enable Imaging Applications

High-end video applications require flexible memory solutions, with sufficient on-chip memory resources and a high-performance interface to external RAM. Virtex-EM fills both requirements. The XCV812E offers 1,120 kb of block RAM to support image buffering, and 301K bits of distributed RAM for pixel manipulation. If more RAM is required, Virtex-EM provides a high performance interface to 266 MHz Double Data Rate (DDR) external memory. The Virtex-EM architecture also provides features to support advanced imaging and graphics applications. LVPECL differential signaling provides a 160 MHz clock source for HDTV. For image processing, general purpose two-dimensional filters with kernel masks of up to 63 x 63 pixels and 12-bit pixel resolution fit into a single XCV812E device that can process 60 1024 x 1024 video frames per second. The Virtex-EM family also supports emerging MPEG-4, JPEG2000, and HDTV standards.

Related Application Note:

Virtex-EM FIR Filter for Video Applications

Leading-Edge Software and Intellectual Property (IP) Support

The Virtex architecture was designed in conjunction with our synthesis partners in order to assure maximum performance, predictability, and simplified integration of intellectual property. The Xilinx solution includes complete Virtex series support in Alliance Series™and Foundation Series™ software. This environment increases productivity by supporting team-based design environment, through Xilinx Internet Team Design, and in the Alliance Series supports third party signal analysis tools which ensures clean signal integrity. Smart-IP™ technology is available to speed time to market, including CORE Generator™ tools that enable high design productivity. Also available are BaseBlox™ cores that have been highly optimized for performance and utilization as well as over 30 Xilinx LogiCORE™ and AllianceCORE™ products, including FIFOs, multiplexer, coders, decoders, and FFTs, that support network switch, ATM, and imaging applications.

Virtex-E Extended Memory Family

		XCV405E	XCV812E
CLB (Rows x Columns)		40x60	56x84
Logic Cells		10,800	21,168
Memory Blocks		140	280
True Dual-Port BRAM (kb)		560	1,120
Distributed RAM (kb)		153	301
Maximum I/O		404	556
DLLs		8	8
Pkg	Size
BG560	42.5x42.5 mm	404	404
FG676	27x27 mm	404
FG900	31x31 mm		556