SelectI/O Technology

In recent years, a large number of new and specialized signaling standards tailored for specific applications have emerged, each with its own specifications for current, voltage, and termination techniques. The Virtex series addresses this problem by building configurable I/O structures that can interface to many different standards. These include Stub Series Transceiver Logic (SSTL) and High Speed Transceiver Logic (HSTL) to connect with fast 3.3-volt and 2.5-volt memories, and the Advanced Graphics Port (AGP) to interface with the Intel Pentium II processor for graphics applications.

The Virtex series also supports the Gunning Transceiver Logic (GTL and GTL+) I/O standards designed to interface with high performance microprocessors and backplanes. The Virtex SelectI/O feature also supports high-speed busses such as PCI33 and PCI66, which require specific current versus voltage characteristics.

These I/O standards solve performance issues, but some of them require specialized output and input buffers on the board. With the Virtex series, up to eight different voltage and signal standards can be directly connected to a single Virtex device.

Direct interfacing with these I/O standards eliminates the need for external buffers, increases performance, cuts costs, and reduces board space.

Virtex SelectI/O technology facilitates high-performance connectivity to leading-edge devices employing multiple voltage and signal standards, simultaneously.

SelectI/O Application Notes

Using the Virtex Select I/O

SelectI/O+ Technology: Flexibility, High Bandwidth and Superior Signal Integrity (Virtex-E)

In order to meet the bandwidth requirements, electrical signals need to travel on a printed circuit board over 100 MHz, standard TTL and CMOS signal technology cannot keep pace. With the Virtex series, Xilinx pioneered the SelectI/O technology designed to support 200 MHz I/O and allow a single device to interface to any device without external converters. Virtex-E SelectI/O+ technology expands the performance and flexibility by supporting high performance I/O standards such as HSTL and SSTL at over 311 Mbps per second per pin. In addition, Virtex-E devices are the first programmable logic device to directly interface to differential I/O standards including LVDS, Bus LVDS (BLVDS) and LVPECL. The Virtex-E family offers a hierarchy of differential support, including up to 36 I/O pairs for LVDS and LVPECL operating at 622 MHz, and up to 344 differential pairs operating at over 311 MHz. Support for up to 340 differential pairs capable of over 311 MHz provides maximum bandwidth of over 100 Gbits/sec, which can be distributed over the three differential signal standards as needed. For the first time in a programmable device, system designers can leverage the high bandwidth and noise immunity characteristics of these standards.

Differential Signaling: LVPECL, LVDS, and Bus LVDS (Virtex-E)

Typical aggregate bandwidth requirements for leading edge systems are exceeding 100 Gbits per second. Increasingly, leading systems designers are turning to differential signaling as the mechanism of choice for these requirements. Differential signaling enables high bandwidth while reducing power, increasing noise immunity, and decreasing EMI emissions. Virtex-E devices meet this emerging challenge with unprecedented capabilities and support for high-performance differential signaling. Virtex-E SelectI/O+ technology addresses the three leading industry-standard differential signaling standards: LVPECL, LVDS, and Bus LVDS (BLVDS).

LVPECL I/O is widely used in 100+ MHz inter-chip signaling in high-speed data communications and instrumentation systems. Fiber-Optic Network Interfaces and gigahertz Analog-to-Digital Converters, for example, rely on LVPECL I/O to achieve gigabit per second bandwidth. All Virtex-E I/Os support LVPECL input, output, and I/O signaling. This unparalleled flexibility enables users to create interfaces to hundreds of industry-standard LVPECL devices.

In addition to high-speed interfacing, LVPECL is the industry standard for transmission of precise, on-board clocks at frequencies in excess of 100 MHz. While traditional LVTTL clock sources are typically limited to 100 MHz and below (due to the fundamental signal integrity limits), LVPECL clock sources provide operation up to 400 MHz. As FPGA system clock frequencies exceed 100 MHz, LVPECL clocking becomes an essential requirement. The Virtex-E device supports high-performance LVPECL clock inputs for global and local clocking, with frequencies in excess of 300 MHz. In addition, through the use of its multiple DLLs coupled with SelectI/O+ technology, the Virtex-E devices enable zero-delay conversion of precise LVPECL clocks into virtually any required I/O standard. This facilitates the use of Virtex-E FPGAs as an integral part of high-performance board-level clock distribution strategies.

In addition to LVPECL, the Virtex-E family has the industrys first programmable devices to support Low-Voltage Differential Signaling (LVDS). LVDS exists in two commonly available variants, LVDS and Bus LVDS. LVDS is optimized for high-speed point-to-point links, while Bus LVDS is optimized for backplane applications employing Multi-Drop (One Transmitter, Multiple Receiver), and MultiPoint (Multiple Transmitters and Receivers) configurations. The Virtex-E device provides unparalleled support for both LVDS and Bus LVDS, with support on all devices and speed grades, and up to 688 pins (344 pairs) of LVDS and/or Bus LVDS capabilities on the largest device, providing an aggregate bandwidth in excess of 100 Gbps. The Virtex-E Bus LVDS I/Os are fully compatible with industry-standard Bus LVDS devices from National Semiconductor and other vendors.

For more information on termination resistors for differential signaling, see Bourns, Inc.

See the LVDS Tech Topic, for more information on LVDS.

LVPECL, LVDS, and Bus LVDS Application Notes& Reference Designs
Multi-channel 622 MHz LVDS Data Transfer with Virtex-E Devices(Virtex-E)		Reference Design
Virtex-E :LVDS Drivers & Receivers: Interface Guidelines (Virtex-E)
Multi-Drop LVDS With Virtex-E FPGAs (Virtex-E)
The LVDS I/O Standard (Virtex-E)

Summary of Standards Supported

Virtex/Virtex-E supports 20 I/O standards as illustrated in the chart below. This allows system designers to interface to any device with zero translation delay. The SelectI/O feature reduces system cost by eliminating external translators, and enabling the lowest power design possible. The SelectI/O interface is also configurable, and can be used to support any new future standards, as well as adapt to any board layout.

Standard	VCCO	Vref/ Swing	Application	Standard Definition
LVTTL	3.3	na	General purpose	Low voltage transisitor-transistor logic
LVCMOS**	1.8	na	General purpose	Low voltage complementary metal-oxide semiconductor
LVCMOS	2.5	na	General purpose	Low voltage complementary metal-oxide semiconductor
LVCMOS*	3.3	na	General purpose	Low voltage complementary metal-oxide semiconductor
PCI 33MHz 3.3V	3.3	na	PCI	Peripheral component interface
LVDS**	2.5	na	Point to point and multi-drop backplanes, high noise immunity	Low voltage differential signal
BLVDS**	2/5	na	Bus LVDS backplanes, high noise immunity, bus architecture backplanes	Bus low voltage differential signal
LVPECL**	3.3	na	High performance clocking, backplanes, differential 100MHz+ clocking, optical transceiver, high speed networking and mixed-signal interfacing	Low voltage positive emitter couple logic
PCI 33MHz 5.0V*	3.3	na	PCI
PCI 66MHz 3.3V	3.3	na	PCI
GTL	na	0.80	Backplane	Gunning transceiver logic interface to processors or backplace driver
GTL+	na	1.00	Backplane
HSTL-I	1.5	0.75	High Speed SRAM	High speed transceiver logic
HSTL-III	1.5	0.90	High Speed SRAM
HSTL-IV	1.5	0.90	High Speed SRAM
SSTL3-I	3.3	1.50	Synchronous DRAM
STTL3-II	3.3	1.50	Synchronous DRAM	Stub-series terminated logic interface for SDRAM
SSTL2-I,II	2.5	1.25	Synchronous DRAM
AGP	3.3	1.32	Graphics	Advanced graphics port
CTT	3.3	1.5	High Speed Memory	Center tap terminated

*Not applicable to Virtex-E family
**Applicable to Virtex-E family only

Customer Comments

"We did an exhaustive search and found that only the Xilinx Virtex FPGAs could provide us with the performance and density necessary to add Gigabit capability to the Nebula switch family, said John Peters, vice president of development at Performance Technologies. We are very impressed with the system level capabilities of the Virtex FPGAs, particularly the digital delay locked loops and support for multiple I/O standards."

"These million gate FPGAs enable our test modules to provide thousands of continuous measurements at telecom speeds up to 2.4 gigabits per second," said Carl Uyehara, vice president of engineering at Adtech, Inc., a leading supplier of broadband test systems. "We especially like the fact that Virtex FPGAs are programmable. This allows us to use a single test module for multiple transmission technologies such as ATM and frame relay, which provides huge cost savings and convenience for our customers plus future enhancement capability."

PCI

PCI (Peripheral Component Interconnect) has become one of the most popular bus standards, not only for personal computers, but also for industrial computers, communication switches, routers, and instrumentation. It solves a wide range of compatibility problems and performance limitations that were encountered with the older ISA and VME standards.

However, PCI is also a significant design challenge; the stringent electrical, functional, and timing specifications are difficult to meet in any technology-and the standard keeps evolving to meet the dynamic needs of our industry. That's why you need a flexible PCI solution that will meet both your current and future requirements, while guaranteeing full PCI compliance with no limitations on performance or functionality.

Our first LogiCORE PCI product was released in January, 1996. Now, our PCI cores have been proven in over 1000 customer designs, clearly demonstrating that Real-PCI from Xilinx is the most flexible and cost-effective solution for your fully-compliant, high-performance PCI system.

The Complete PCI LogiCore PCI Solution includes:
- 64-bit, 66 MHz PCI for Virtex
- 32-bit 33 MHz PCI for Virtex
- PCI64 Virtex (0-66 MHz)
- PCI32 Virtex

PCI Configuration Tool

Customer Comments

With the Real-PCI 64/66 products from Xilinx, we were able to implement a fully compliant PCI interface in our new Mx2/PCI product family plus other functions such as direct memory access (DMA), four dual-port FIFOs, and 200,000 gates of our own unique design in a single device, said John Beck, principal engineer at DOME Imaging Systems, Inc., Waltham, Mass. The Dome Mx2/PCI is the first in a new family of high resolution display controllers for the medical imaging market that can handle transfers of over 500 Mbytes/sec from the host. After evaluating different solutions in the market, we found that only Xilinx could meet the demand requirements for full 66 MHz PCI compliance, Beck said.