The Quarterly Journal for 
Xilinx Programmable Logic Users
Xcell 29 - Third Quarter, 1998



Products
Development System
Special Section on Verification
Hints & Issues

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In this Q3 '98 issue...

Products

Editorial: Moving Towards a Perfect World
New Chip-Scale Packaging: Ideally Suited to Today's Portable and Small Form-Factor Applications
New Spartan -4 Devices for High Speed Applications
The New XC95144: 50% Smaller
Xilinx Unveils New "QPRO" Products for Aerospace, Defense, and High Reliability Markets

Customer Success Stories

PCI Reconfigurable Image Advanced Processor (PRIAP)
Esaote Biomedica: A Spartan Success Story
The KATSYS8010 CNC Controller from KAT GmbH
KAT GmbH: Using Xilinx XC5210 FPGAs For a Dual Incremental Encoder and Synchronous Serial Interface Controller (DISSIC)

Development System

pdf The Core Story: A Breakthrough in Time to Market
pdf The Low-Cost PCI Solution
pdf New XC9500 CORE Support
pdf Full-Featured Xilinx CPLD Starter Kit for $99.00 from Insight Electronics
pdf DSP Design Tools for Xilinx FPGAs
pdf Synplify Extends Timing Constraint Control for Mixed Entry
pdf FPGA Design Cycle Time Reduction and Optimization
pdf Device Programmer Support
 

Special Section on Verification

pdf Verification for Higher Productivity
pdf Using Synopsys SmartModel FPGA Models to Verify Xilinx FPGA Designs
pdf Mixed Schematic and HDL Design Entry
pdf Verifying PCI Designs
pdf Viewlogic's Mixed-Design Verification Methodology
pdf The Basic Elements of HDL Simulation for FPGAs and CPLDs
pdf Board Design and Simulation Using OrCAD Express
Post-Route Timing Analysis with Leonardo Spectrum
pdf Verification Using a Self-Checking Test Bench
HDL Verification: 
We Will Take You to The Leaders

Hints and Issues 

pdf Looking for the Best HDL Design Flow?
pdf In-Stat Analyst to Discuss ASIC Issues
pdf HDL Advisor: How to Use the Clock Enable Pin Instead of Gated Clocks in HDL Designs
pdf Q&A: Foundation, Model Technology
pdf Q&A: HDL State Machine Technique
pdf Q&A: Boundary Scan EXTEST
 

 
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