The Quarterly Journal for 
Xilinx Programmable Logic Users
Xcell 31 - First Quarter, 1999 
New Technology 
Applications 
Success Stories
Product Information 
Hints & Issues 
News Briefs

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In this Q1 '99 issue... 

New Technology

Imagination Springs to Life... 
The New Virtex FPGA Family - Much More Than Just a Million Gates 
New Internet Reconfigurable Logic for Creating Web-enabled Devices 

Applications

Reed-Solomon Cores Excel in the Virtex Architecture 
Creating Efficient Multi-Tap Shift Registers in Virtex LUTs 
Designing with Large, Fast Programmable Logic Devices 
Efficient Multi-Channel Serial to Parallel Converter 
New ASIC Estimator For Cost Modeling 
See also: ASIC Estimator 
FPGA-Link - System Level Integration of FPGAs 
New Virtex Card Provides FPGA-based Real Time Processing 
pdf Hierarchy Management in Synplify 
pdf Anna-Liz: A New Core for Debugging PCI Designs 
pdf New CardBus and PCMCIA Cores for Xilinx FPGAs 
pdf Concept HDL - New Standard 

Success Stories

pdf Using the Xilinx Verilog Flow for Efficient High Speed Design 
pdf A PCI Acquisition Board Using the XC4013 

Product Information

pdf CPLD Fitter Shootout: Xilinx 1.5 versus Altera 9.01 
XC9500XL CPLDs Immune to Power Sequencing Problems 
Frequency Synthesis Techniques 
pdf JTAG Boundary Scan for Low Cost System Testing 

Hints & Issues

pdf HDL Advisor - Creating the Most Efficient Comparators 
pdf Hotline Q&A: Virtex 
pdf Virtex I/V Curves for Various Output Options 

News Briefs

pdf 1 GHz Performance Milestone - 0.18m, 1.8V FPGA 
pdf Trade Show Programs 
See also: Trade Shows 
pdf Technical Support - support.xilinx.com