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Xilinx Design Reuse

Design Reuse Introduction Design Reuse Tools
[]Overview
[]FAQ		 [] Xilinx IP Remote Interface
[] Xilinx IP Internet Capture
Design Reuse Documentation Other Links
[] Xilinx Design Reuse Methodology[PDF] []Press Release
[]Xilinx IP Center
[]Xilinx CORE Generator System

Xilinx Design Reuse Overview

The need for design reuse has been apparent for many years; no company likes to put many man years of effort into a design that can be used only once. Today, thousands of designers are creating intellectual property (IP) on a huge scale, targeting the widely popular million-gate Virtex!" FPGA family which is ideally suited to support design reuse.

 [IP Internet Capture]
This web site has been created to meet this fast growing demand for reusable IP and IP management tools. Xilinx is addressing some of these Design Reuse issues with two new tools, the IP Internet Capture and IP Remote Interface tools and an FPGA design reuse manual. The intent of these tools and manual is to help design teams implement designs for reuse and share their intellectual property internally and over the web.

FPGA Supplement to Reuse Manual

The new Xilinx Design Reuse Methodology for ASIC and FPGA Designers manual is intended for designers who want a common strategy for reusing intellectual property, regardless of whether it was developed for ASICs or for FPGAs. The Xilinx supplement to the Synopsys and Mentor Graphics RMMInternet Link manual provides an overview of FPGA system level features and contains general RTL synthesis coding guidelines that have the most impact on improving system performance. The guidelines and coding styles presented are built upon the discipline of good design. By coding with these guidelines an ASIC designer will find that they have improved their ASIC code as well as creating an FPGA friendly implementation.

IP Remote Interface

The IP Remote Interface tool, which is a new feature of the Xilinx CORE Generator system, allows an IP developer to create parameter-driven cores. These Cores can be added to the IP catalog in the Xilinx CORE Generator system. An IP developer can even have these cores launch an application over the web.

IP Internet Capture

The new IP Internet Capture tool, provides designers with an automated method to identify, capture, and document a core. This core can take the form of synthesizable VHDL or Verilog code, or a fixed function netlist. It even creates a web page with links to download the packaged core. This core can be shared over a customer's network on internal or external web sites. Once the new module has been captured and posted, other engineers can use a standard Internet browser to download the IP and install it in their copy of the Xilinx CORE Generator system.

 [IP Internet Capture]

The Xilinx IP Internet Capture toolInternet Link is available for download from the Design Reuse Resource Lounge. To access this lounge you will need to register.

  • If you already have a Xilinx Web ID and Password, but need to register Click HereInternet Link.
  • If you need to get a Xilinx Web ID and Password Please Click Here and fill out the registration from.

Comments, Questions, Problems, Please E-mail DesignReuse@xilinx.com