Virtex Series FPGAs System Memory

Technical Briefs System Memory    Memory Vendors Supported  Virtex SDRAM Controller Design Virtex ZBT SRAM Controller Design  True Dual-Port Embedded Block Memory    CAM Double Data Rate SDRAM   Tools ZBT SRAM Timing Calculator   to view the  PDF files below.

Customer Testimonials What Customers Think About Memory Hierarchy Features

Misc. Application Notes		Reference Designs
	Data-Width Conversion FIFO's Using the Virtex Block SelectRAM Feature	PC:Verilog UNIX:Verilog
	170 MHz Synchronous and Asynchronous FIFOs Using the Virtex Block SelectRAM+	PC: VHDL & Verilog UNIX: VHDL & Verilog
	Using the Virtex SelectRAM+
	Parameterizable Distributed RAM for Virtex -VHDL (Virtex)	VHDL
	All Other Virtex Application Notes	All Other Reference Designs

System Memory Technical Brief 

Beyond the obvious benefits of speed and size, the Virtex FPGAs offer enhanced memory-related advantages for both on chip as well as external.  The SelectRAM+ memory hierarchy includes: 

• Distributed SelectRAM 
• Block SelectRAM 
• High-Speed Memory Interfaces 

    
 
Virtex FPGAs provide access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip Distributed SelectRAM and Block SelectRAM, a Virtex design can also interface directly to megabytes of external high-speed SRAMs and DRAMs. The combination of high speed SelectI/O™ and on-chip Clock Delay-Locked Loop (DLL) allows systems to operate at maximum RAM speeds. A Virtex interface to a ZBT (Zero Bus Turnaround*) SRAM provides interleaved Read/Write messages without wasteful turnaround cycles. 
 

Distributed SelectRAM 

Block SelectRAM 

High-Speed Memory Interfaces 

The third part of the Virtex memory hierarchy comprises pre-engineered interfaces to off-the-shelf memory parts from leading memory vendors. The combination of high speed SelectI/O and on-chip CLKDLL enable the interface to operate at maximum RAM speeds. Off-chip memory solutions for Virtex design currently include interfaces to ZBT (Zero Bus Turnaround) SRAM (Pipelined and Flowthrough), SDRAM, and SGRAM reference designs. The pre-engineered solutions incorporate a synthesizable Verilog net list, timing constraints in the Xilinx UCF format, and special switches for software where applicable. 
 

Memory Vendors Supported

Virtex and Virtex-E FPGAs support some of the most advanced memories on the market today. Through close relationships with memory vendors, we are able to ensure support for their memory devices through future generations. The table below illustrates some of the vendors supported:

Memory Vendors

Integrated Device Technology (IDT)

Micron Technology

Samsung Semiconductor

Virtex SDRAM Controller Design 

SDRAM controllers vary significantly in features, complexity, and performance. Xilinx provides an application note describing common issues faced by designers designing an SDRAM controller. The reference design, written in Verilog HDL language, is easily modified to fit different memory organization or processor speed and bandwidth requirements. Some programmable interface features that are supported in the SDRAM controller are described in the application note.  They can be implemented without requiring a change in the Verilog code. Other less popular features are not programmable and will require a code change. Design trade-off and features for the current SDRAM controller are listed below. 

• Only normal operation mode is supported 
• Multiple bank utilization increases bandwidth 
• Burst length applies to both Read and Write operations 
• Sequential burst types of lengths 1, 2, 4, or 8 can be programmed during operation without resetting the controller or SDRAMs 
• CAS Latencies of 2 and 3 can be programmed 
• Programmable RAS to CAS delay feature increases performance. 
• 16-bit programmable refresh counter 
• Closed-page policy reduces initial access latency 

Application Notes		Reference Designs
	Virtex Synthesizable High Performance SDRAM Controller	PC: VHDL   PC: Verilog  UNIX: VHDL   UNIX: Verilog

Virtex ZBT SRAM Controller Design 

The ZBT SRAMs are available with LVTTL I/Os. The Virtex SelectI/O supports LVTTL signaling with a range of driver strengths from 2 mA to 24 mA and a choice of fast or slow slew rates.  A ZBT SRAM controller design in synthesizable Verilog for a 64K x 36 pipelined device as well as for a 64K x 36  flowthrough device is provided in the design code. Controllers for other size ZBT SRAMs are easily derived from these designs. In these examples, Read/Write is the only control signal. It is used to control the Tri-state drivers for the 36 bits of data.  In order to run the Virtex Pipelined ZBT SRAM interface at 200 MHz (100 MHz for flow through) it uses CLKDLLs to de-skew and double clock frequency.  During a write operation to the pipelined ZBT SRAM, data must be provided to the RAM two cycles after the Address and Control signals. Assuming that data arrives in lock step with Address and Control, the controller drives the data to the RAM through two pipelined stages. While the control signals to the RAM are sent directly, the control signals inside the controller are delayed through an equal number of pipelined stages to match the data latency. The pipelined example uses a Flip-flop tree to minimize the fan-out for the Read/Write signal, which in turn facilitates high-speed data access.  Virtex SelectI/O provides a wide variety of standards and for LVTTL, it offers a wide range of driver strengths. For more detail of this design, please see the Virtex ZBT SRAM controller reference design page. 
 

Further Information on ZBT SRAM Designs
	ZBT SRAM Timing Calculator
	Synthesizable 200 MHz ZBT SRAM Interface Application Note
	200 MHz ZBT SRAM VHDL Reference Design for PC
	200 MHz ZBT SRAM VHDL Reference Design for UNIX
	200 MHz ZBT SRAM Verilog Reference Design for PC
	200 MHz ZBT SRAM Verilog Reference Design for UNIX

True Dual-Port Embedded Block Memory for Highest Internal Memory Bandwidth 

This diagram shows that in order to emulate most of the functionality of a dual-port memory, two-port memory architectures require twice the number of memory bits and multiplexing of address and data. This results in two-port memory at roughly half the bandwidth and efficiency of the Virtex-E True Dual-Port memory in any given configuration.

Each True Dual-Port memory block supports 4 Kbits of memory. Each port can be configured separately to support a variety of depth/width combinations. Embedded memory can serve to buffer high bandwidth data as well as reduce the internal processing speed by transparently converting from one data width to another. The diagram below demonstrates an OC-192 application example. A data port with OC-192 bandwidth comes in on 32 BLVDS pairs running at 311 Mbits per second per pair. Eight blocks of embedded RAM are used to buffer the data internally. The port taking data from the I/O register to the memory is configured as one Kbit deep by 32. The port leading to the internal processing of the data is configured as 256 by 128. Internal processing of the 128-bit data need only run at 78 MHz to keep up with the OC-192 bandwidth. An outgoing port would be configured similarly. 
 

CAM (Content Addressable Memory)

A Content Addressable Memory is a storage array designed to quickly find the location of a particular stored value. By comparing the input against the data memory, a CAM determines if an input value matches one or more values stored in the array. If the comparison is done simultaneously, the CAM is said to be at maximum efficiency. A match, when it exists, is found in one clock cycle.

Similar to a RAM, a CAM stores words in an array. The write mode is comparable, but the read mode is different. In a RAM, the word in a specific location is read by the address. In a CAM, the data on the input is looking for a match. When a match is found, the output is the address in the array.

The number of address lines limits a RAMs data size. For example, a 10-bit bus addresses 1024 locations of 8-bit data. A CAM does not have this limitation because it does not use an address bus to read a location. To find a match of an 8-bit value in 1024 locations, an 8-bit bus on the input is required. When the data is found in the CAM, a match signal goes active. The output is the matching data address. Because a CAM does not need address lines to find data (read mode), the memory size can be easily extended. The width is determined by the storage and com-parator size.

The basic core of a CAM has a storage location, and a comparator between the storage location value and the input data. This application note describes the different ways to design a basic core optimized for either speed, density, or both.

CAMs are used in telecommunications, networking, Ethernet, ATM switches and diverse protocol applications. To determine the correct CAM implementation for a particular application, the following should be investigated.

• Word Size (width)
• Number of words (depth)
• Matched or compare time (read)
• Importance of write speed (or if it is important)
• Clock frequency
• Masks and outputs

Virtex devices offer the advantage of different approaches to designing an optimal CAM. There is not a specific CAM type to fit all typical CAM applications and different approaches produce an optimal results.

CAM Application Notes and Reference Designs

Application Note		Reference Design
	Using Block SelectRAM+ for High Performance Read/Write CAMs	PC: VHDL&Verilog UNIX: VHDL&Verilog
	CAM in ATM Applications	PC: VHDL UNIX: VHDL
	An Overview of Multiple CAM Designs in Virtex Devices
	Designing Flexible, Fast CAMs with Virtex Slices	PC: VHDL&Verilog UNIX: VHDL&Verilog

Double Data Rate SDRAM

As microprocessors get faster every year, memory architectures are also changing in order to improve the overall system performance. DDR SDRAM and RDRAM (Direct RAMBUS DRAM) are the top two contenders for the next generation of SDRAM.

While RDRAM is a revolutionary change, DDR SDRAM is a natural evolution from the existing SDRAM architecture. RDRAM has a peak bandwidth of 1.6 Gbytes/s with 16-bit lines and a 400 MHz clock frequency. DDR SDRAM also has a peak bandwidth of 1.6 Gbytes/s with 64-bit data lines and a 100 MHz clock frequency.

The main advantage of DDR SDRAMs over RDRAMs is the use of the basic system infrastructure developed for PC-100. This eliminates the numerous design changes required by different "packet" protocols. DDR SDRAM was approved as a JEDEC (Joint Electron Device Engineering Council) standard in February, 1998, and is currently supported by most major SDRAM vendors.

DDR Application Notes and Reference Designs
	Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller
	Reference Design: Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller - 64-bit for PC
	Reference Design: Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller - 64-bit for UNIX
	Reference Design: Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller - 16-bit for PC
	Reference Design: Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller - 16-bit for UNIX

Customer Comments

"The clock frequency of the SDRAM interface is our major bottleneck in providing higher 
bandwidth," said Aptitude Vice President and Chief Technical Officer Russell Dietz. "We plan to  double the clock frequency on the SDRAM interface to 125 MHz by using Virtex delay lock 
loops to de-skew the FPGA clock and the SDRAM clock. Another advantage Xilinx Virtex 
FPGAs offer is their seamless fit into our current ASIC software flow."   

"The Virtex parts were also the most advanced that we could find", says Jim Crysdale, Sr. Staff Engineer & Manager at Qualcomm. "The block memory was very important because we need a lot of storage to store data. Obviously when you’re running data networks you have to store data, and the fact that we had on-chip RAM was very enabling to us."

"Because it is a high density, high capacity device, the Xilinx FPGA allows us to provide very large capacity emulators to meet our customers' needs," said Juergen Jaeger, Director of Emulation Product Management for IKOS. IKOS has traditionally used external memory devices such as SRAM, but are now beginning to take advantage of the internal memory. "The obvious result of using the embedded RAM of the FPGA is an increase in the speed and efficiency of our products. The device allows us to build upon our already successful architecture," said Jaeger.

The availability of large amounts of block SelectRAM in the Vid chip also allowed us to implement many of our sophisticated post-processing algorithms,” said John Snow, PC Simulation Engineering Manager at Evans & Sutherland.  
 
 

More Information  Virtex Overview   System Performance/Bandwidth  System Interface  System Design Tools  Data Sheets  Application Notes

Product Information    Software    IP Center    Hard Copy Literature Request