Xilinx Foundation: Tips and Techniques
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General
Solution 7175 - Foundation F2.1i Install: How to install additional device families
Solution 4292 - Foundation F2.1i,F1.5i: Adding schematics to HDL flow projects
Solution 1518 - Foundation: Changing title block information on schematics
Solution 2599 - Foundation: How to use both XACT6-based and M1-based flows with Foundation
Schematic Editor
Solution 2602 - Foundation, Logiblox: How to make bus pin names visible on Logiblox components
Solution 2603 - Foundation, Logiblox: How to change parameters of existing Logiblox components
Gate-Level Simulation
Solution 1286 - Foundation Simulator: Simulating bidirectional signals
Express Synthesis
Solution 4394 - Foundation F1.5/i: Setting default FSM encoding scheme
Solution 4545 - Foundation F1.5: Important information about revision control in HDL flow projects
HDL Behavioral Simulation
Application Note: Using Model Technology ModelSim with Xilinx Foundation Series Software
(256KB)
XVHDL Synthesis
Solution 4468 - Using Metamor (XVHDL) with Foundation F1.5
XABEL
Solution 4353 - Foundation F1.5: ABEL designs require "Schematic" project type
Solution 2776 - Foundation F1.3/F1.4, XABEL: How to generate .PLD (Plusasm) file from XABEL
Solution 3020 - Supported 'Xilinx Property' statements with CPLDs and XABEL6
State Editor
Solution 3020 - Foundation State Editor: How to modify encoding scheme for State Machine
