Return to the Products Page
  homesearchagentssupportask xilinxmap

Standard DLL Usage

Sparty's Favorite Recipes 007 Kiss Your ASIC Good-bye!

Ingredients:

  • Any Spartan-II Device
  • 2.1i Development System
  • VHDL or Verilog
  • Nutritional Analysis:

  • DLLs: 1
  • Instructions

    The circuit shown below resembles the BUFGDLL macro implemented in such a way as to provide access to the RST and LOCKED pins of the CLKDLL.

    VHDL

    library ieee;
    use ieee.std_logic_1164.all;
    library unisim;
    use unisim.vcomponents.all;

    entity dll_standard is
    port (CLKIN : in std_logic;
    RESET : in std_logic;
    CLK0 : out std_logic;
    LOCKED: out std_logic);
    end dll_standard;

    architecture structural of dll_standard is

    signal CLKIN_w, RESET_w, CLK0_dll, CLK0_g, LOCKED_dll : std_logic;

    begin

    clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
    rstpad : IBUF port map (I=>RESET, O=>RESET_w);

    dll : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK0_g, RST=>RESET_w, CLK0=>CLK0_dll, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open, CLKDV=>open, LOCKED=>LOCKED_dll);

    clkg : BUFG port map (I=>CLK0_dll, O=>CLK0_g);
    clkpad : OBUF port map (I=>LOCKED_dll, O=>LOCKED);

    CLK0 <= CLK0_g;

    end structural;

    Verilog

    module dll_standard (CLKIN, RESET, CLK0, LOCKED);
    input CLKIN, RESET;
    output CLK0, LOCKED;

    wire CLKIN_w, RESET_w, CLK0_dll, LOCKED_dll;

    IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));
    IBUF rstpad (.I(RESET), .O(RESET_w));

    CLKDLL dll (.CLKIN(CLKIN_w), .CLKFB(CLK0), .RST(RESET_w), .CLK0(CLK0_dll), .CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLKDV(), .LOCKED(LOCKED_dll));

    BUFG clkg (.I(CLK0_dll), .O(CLK0));
    OBUF lckpad (.I(LOCKED_dll), .O(LOCKED));

    endmodule

     

    Related Information