Instructions
By connecting two DLL circuits each implementing a 2x clock multiplier
in series as shown below, a 4x clock multiply can be implemented
with zero skew between registers in the same device. When using
this circuit it is vital to use the SRL16 cell to reset the second
DLL after the initial chip reset, so that the second DLL will recognize
the change of frequencies when the input changes from a 1x (25/75)
waveform to a 2x (50/50) waveform.
VHDL
-- DLL 2X and 4X Example
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity dll_standard is
port (CLKIN : in std_logic;
RESET : in std_logic;
CLK2X : out std_logic;
CLK4X : out std_logic;
LOCKED: out std_logic);
end DLL_standard;
architecture structural of DLL_standard is
signal CLKIN_w, RESET_w, CLK2X_DLL, CLK2X_g, CLK4X_DLL,
CLK4X_g : std_logic;
signal LOCKED2X, LOCKED2X_delay, RESET4X,
LOCKED4X_DLL : std_logic;
signal logic1 : std_logic;
begin
logic1 <= '1';
clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF port map (I=>RESET, O=>RESET_w);
dll2x : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK2X_g, RST=>RESET_w,
CLK0=>open, CLK90=>open, CLK180=>open,
CLK270=>open, CLK2X=>CLK2X_DLL, CLKDV=>open,
LOCKED=>LOCKED2X);
clk2xg : BUFG port map (I=>CLK2X_DLL, O=>CLK2X_g);
rstsrl : SRL16 port map (D=>LOCKED2X, CLK=>CLK2X_g, Q=>LOCKED2X_delay,
A3=>logic1, A2=>logic1, A1=>logic1, A0=>logic1);
RESET4X <= not LOCKED2X_delay;
dll4x : CLKDLL port map (CLKIN=>CLK2X_g, CLKFB=>CLK4X_g, RST=>RESET4X,
CLK0=>open, CLK90=>open, CLK180=>open,
CLK270=>open, CLK2X=>CLK4X_DLL, CLKDV=>open,
LOCKED=>LOCKED4X_DLL);
clk4xg : BUFG port map (I=>CLK4X_DLL, O=>CLK4X);
lckpad : OBUF port map (I=>LOCKED4X_DLL, O=>LOCKED);
CLK2X <= CLK2X_g;
CLK4X <= CLK4X_g;
end structural;
Verilog
// DLL 2X and 4X Example
//
module DLL_standard (CLKIN, RESET, CLK2X, CLK4X, LOCKED);
input CLKIN, RESET;
output CLK2X, CLK4X, LOCKED;
wire CLKIN_w, RESET_w, CLK2X_DLL, CLK4X_DLL, LOCKED2X;
wire LOCKED2X_delay, RESET4X;
wire logic1;
assign logic1 = 1'b1;
IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));
IBUF rstpad (.I(RESET), .O(RESET_w));
CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK2X_DLL), .CLKDV(), .LOCKED(LOCKED2X));
BUFG clk2xg (.I(CLK2X_DLL), .O(CLK2X));
SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay),
.A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
assign RESET4X = !LOCKED2X_delay;
CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK4X_DLL), .CLKDV(), .LOCKED(LOCKED_DLL));
BUFG clk4xg (.I(CLK4X_DLL), .O(CLK4X));
OBUF lckpad (.I(LOCKED_DLL), .O(LOCKED));
endmodule
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