CSCI 4717 -- Computer Architecture
Test 3 Study Guide
First of all, I have provided a number of old tests to help
you study. When you look at the old tests, be sure to check if the topic that
a particular question addresses is included in the list of topics below. Do not
panic when you see a question that doesn't make sense or if you think it pertains
to an earlier test. Only the topics listed below will be on
the test. Also, memory management was covered on test 2 in tests before 2005, so be sure to go back to those when you want to see more sample
problems on memory management.
The following is a list of the topics that we've covered since the second test,
topics which you will see on the third test. Look for the format
of the third test to be alot like that of the first and second tests.
- Memory Management
- Reading: Stallings section 8.3
- Review slides 11 through 36 of lecture:
- Review the following problems from textbook:
- Review questions 8.5 through 8.10
- Problems 8.7 and 8.10
- Important topics:
- Virtual memory and paging
- Virtual memory
- Thrashing
- Benefits of virtual memory
- Don't need all of a process in memory to run it
- Swap in pages as required (real-time)
- Can run processes that are larger than available memory
- User program sees much bigger memory
- Page table structure and operation (Understand VAX example on page
264)
- Translation Lookaside Buffer
- Segmentation
- CPU Registers
- Reading: Sections 10.1, 10.2, 12.1, and 12.2
- Review slides 1 through 35 of lecture (Be sure you understand the 0-3 address operations discussed in slides
8 through 17):
- Review the following problems from textbook:
- Ch. 10 Review questions 10.1, 10.3, 10.4, 10.5, 10.8, 10.9, and 10.14
- Ch. 10 Problems 10.6, and 10.8
- Ch. 12 Review questions 12.1 through 12.4
- Problems 12.1 and 12.2
- Important topics:
- Components of assembly instructions, Figure 10.1 --
(Op code, source operand(s), result reference, next instruction reference)
- Locations of operands -- main or virtual memory, CPU register, I/O
device
- Design of an Instruction Set
- Design concerns (number of operands, complexity, data types,
instruction formats, number of addresses, number of registers,
which operations can be performed on which operands, addressing
modes)
- CISC issues and tradeoffs
- RISC issues and tradeoffs
- Wulff's attributes of a good instruction set:
- Complete: be able to construct a machine-level program to evaluate
any computable function
- Efficient: frequently performed functions should be done quickly
with few instructions
- Regular and complete classes of instructions: provide "logical"
set of operations
- Orthogonal: define instructions, data types, and addressing
independently
- Additional attribute: Compatible: with existing H/W and S/W
in a product line
- Addressing
- Tradeoffs of different numbers of operands
- 3 operand/address machines
- 2 operand/address machines
- 1 operand/address machines
- 0 operand/address machines (stack machine)
Processor and register organization
- Steps in the execution of an instruction
- Types of registers and their purpose
- CPU Pipelines
- Reading: Sections 12.3 and 12.4
- Review slides from lecture:
- Review the following problems from textbook:
- Review questions 12.5 through 12.7
- Problems 12.7, 12.8, 12.12, and 12.13
- Review pipeline homework assignment
(answers)
- Important topics:
- Instruction cycle -- Be able to describe the execution of an instruction
using Figure 12.5
- Pipeline strategies
- Prefetch
- Break instruction into smaller pieces -- Figure 12.5
- Be able to explain Figures 12.10, 12.11, 12.12, and 12.13
- Be able to discuss problems such as:
- bus contention
- branching
- overhead involved in moving data from stage to stage (buffer
to buffer)
- additional control logic needed to handle memory and register
dependencies with increased number of stages
- Equations 12.1 and 12.2
- Data dependencies (also covered in chapter 13)
- Dealing with branches
- Mulitple streams
- Prefetch branch
- Loop buffer
- Branch prediction (also understand Figures 12.16 and 12.17)
- Delayed branch (actually, this comes from chapter 13 too)
- RISC Processors
- Reading: Chapter 13
- Review slides from lecture:
- Review the following problems from textbook:
- Review questions 13.1 through 13.5
- Problems 13.1, 13.2, and 13.5
- Review RISC homework assignment (answers)
- Important topics:
- Drives behind development of RISC, i.e., problems with CISC implementations that support RISC architecture
- How to test performance in RISC versus CISC
- General characteristics of programs, i.e., understand the needs
and implementations of the following types of program components (don't
worry about memorizing statistics presented in the book)
- assign
- loops
- procedures and passing arguments to them
- if
- goto
- Register use
- Hardware methods
- Register windows and handling local and global variables
- Compare and contrast register windows with instruction cache
- Software methods -- graph coloring
- Drives behind limited/simple instruction set
- One instruction per cycle
- Register-to-register operations
- Simple addressing modes
- Simple instruction formats
- Optimization of pipeline due to better instruction design
- Be able to explain Figures 13.6 and 13.7
- Understand benefits of RISC pipeline over CISC
- Delayed branch
- Delayed load
- Intstruction-Level Parallelism -- Superscalar processors
- Reading: Sections 14.1 and 14.2
- Review slides from lecture:
- Review the following problems from textbook:
- Review questions 14.1 through 14.4 and 14.6 through 14.8
- Problems 14.1 and 14.5
- Review superscalar homework assignment (answers)
- Important topics:
- Characteristics of instruction-level parallelism
- Limited by data dependency -- types include
- True data dependency (Figure 14.3)
- Procedural dependency (Figure 14.3)
- Resource conflicts (Figure 14.3)
- Output dependency (Figure 14.4b)
- Antidependency (Figure 14.4c)
- Design issues
- In-order issue with in-order completion
- In-order issue with out-of-order completion
- Out-of-order issue with out-of-order completion
- Register renaming
- Branch prediction and delayed branch issues
- SMP and Clusters
- Reading: Sections 18.1 through 18.3 and 18.5
- Review slides from lecture:
- Review the following problems from textbook:
- Review questions 18.1 through 18.8
- Important topics:
- Types of Parallel Processor systems (Figures 18.1 and 18.2)
- Single instruction, single data stream (SISD)
- Single instruction, multiple data stream (SIMD)
- Multiple instruction, single data stream (MISD)
- Multiple instruction, multiple data stream (MIMD)
- Symmetric Multiprocessors (shared memory - tightly coupled)
- Characteristics
- O/S Issues
- General configuration
- Bus configurations
- Time shared
- Multiport memory
- Central control
- Cache coherence
- Software solutions
- Hardware solutions (directory protocols & snoopy/MESI
protocols)
- Table 18.1 and Figure 18.7
- Clusters (distributed memory - loosely coupled)
- Characteristics
- Benefits
- Configurations
- High-speed message link options
- Shared disk
- Secondary server
- Separate Server
- Shared nothing
- Shared disk
- O/S Issues
- Components of middleware (multiple components to each)
- Create unified image to user
- Enhancement of availability
- Cluster versus SMP
- Both provide multiprocessor support to high demand applications
- Both available commercially – SMP for longer
- SMP is easier to manage and control
- SMP is closer to single processor systems
- SMP scheduling is main difference
- SMP uses less physical space
- SMP has lower power consumption
- Cluster has superior incremental & absolute scalability
- Cluster has superior availability – Redundancy
- Cluster is simpler to create from computers than SMP which is designed from PCB level