Subject: Voting Guidelines - further information
From: Yatin Trivedi (trivedi@pacbell.net)
Date: Fri Sep 27 2002 - 17:21:42 PDT
Hello committee members,
Here is the remaining information that I promised-
List of attendees with their voting eligibility:
[xxx-xx] Ghassan Khoory (Synopsys)
[xxx-xx] Kevin Cameron (NSC)
[xxx-x-] Simon Davidmann (Co-Design)
[xx-xx-] Peter Flake (Co-Design)
[xxxxxx] Joao Geada (Synopsys)
[x-----] Tayung Liu (Novas)
[xxxxx-] Andrzej Litwiniuk (Synopsys)
[x-----] Mike McNamara (Verisity)
[xxx---] Stuart Swan (Cadence)
[--xx-x] Francoise Martinole (Cadence)
[-xxxxx] Bassam Tabbara (Novas)
[--xxxx] Yatin Trivedi (ASIC Group)
[--xx-x] Michael Rohleder (Motorola)
[--x---] Darryl Parham(Sun)
[---x-x] Alain Reynaud (Tensilica)
[-----x] Tarak Parikh (@HDL)
[-----x] John Stickly (Mentor)
[-----x] Swapanjit Mitra (SGI)
Applying the rules of voting (as I sent yesterday), the following
companies are eligible to vote:
Cadence
Motorola
Novas
Synopsys
I did not list Co-Design because it has become part of Synopsys.
Others are not members of Accellera (based on what I have checked).
If any of you believe that your current involvement in IEEE
or past effort in System Verilog 3.0 makes you eligible to vote
(and meet attendance requirement) please let me know so I can
include you in voting process.
There is only one vote for each company. For companies with more
than one participant, please identify a representative so that
the vote comes from the person representing the company.
Considering the lateness of this email, I would like to extend the
deadline for voting to Monday, 9/30/02 6:00pm PST. Please let me know
if you see any difficulty with this.
We will discuss the vote and further activities on Tuesday, 10/1/02.
Regards
Yatin
Yatin Trivedi trivedi@asicgroup.com
The ASIC Group (408) 761-0262
www.asicgroup.com (408) 223-1231
Silicon Valley's Design & Verification Team
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