Subject: SSUE:DirectC:Name resolution between a Verilog task and a DirectC exte rnal C function.
From: Swapnajit Mittra (mittra@juno.com)
Date: Sat Oct 19 2002 - 21:52:43 PDT
ISSUE:DirectC:Name resolution between a Verilog
task and a DirectC external C function.
I propose: A Verilog task or function shall override
an external C function by the same name within the
scope of the module where this task or function
is located.
I believe this is already the case in VCS. I
propose SV-CC makes this part of the requirement
for DirectC i/f as this provides control to each
Verilog module to re-define a task within its
boundary.
- Swapnajit.
-- Swapnajit Mittra http://www.angelfire.com/ca/verilog
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