Subject: Re: SSUE:DirectC:Name resolution between a Verilog task and a DirectC exte rnal C function.
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Oct 21 2002 - 10:06:57 PDT
> From owner-sv-cc@server.eda.org Sat Oct 19 21:57:33 2002
> X-Original-From: "Swapnajit Mittra" <mittra@juno.com>
> To: sv-cc@server.eda.org, mittra@juno.com
> cc:
> Subject: SSUE:DirectC:Name resolution between a Verilog task and a
> DirectC exte rnal C function.
> From: "Swapnajit Mittra" <mittra@juno.com>
>
> ISSUE:DirectC:Name resolution between a Verilog
> task and a DirectC external C function.
>
> I propose: A Verilog task or function shall override
> an external C function by the same name within the
> scope of the module where this task or function
> is located.
>
> I believe this is already the case in VCS. I
> propose SV-CC makes this part of the requirement
> for DirectC i/f as this provides control to each
> Verilog module to re-define a task within its
> boundary.
>
> - Swapnajit.
>
>
> --
> Swapnajit Mittra
> http://www.angelfire.com/ca/verilog
That would also be covered by taking the approach that modules
are like C++ classes and their functions and tasks are virtual
wrt linking.
Kev.
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