Subject: Re: Modified Proposal ... - modified syntax for "export"
From: Stickley, John (john_stickley@mentorg.com)
Date: Fri Nov 22 2002 - 10:09:35 PST
Andrzej,
Andrzej Litwiniuk wrote:
So, if I understand you correctly is this allowed ?
module outer;
...
module inner;
...
endmodule
endmodule
OK. So I guess the intent must have been that a nested scope SV module
has the same semantics and purpose as a nested VHDL "block" statement.
So we agreed to get rid of "as" and "function". Good.
Now, the controversy got narrowed down to the order ('cname fname' vs.
'fname cname')
and quotes. Either order is fine for me. Regarding quotes, I disagree
with
"less trouble to parse", same trouble or the lack of, but whatever.
I can accept either version.
Andrzej
Splendid. So I'll update the propsal to show Kevin's syntax with
allowances
for interfaces as you described.
-- johnS
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