Subject: Re: Modified Proposal ... - modified syntax for "export"
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Nov 22 2002 - 10:34:15 PST
Stickley, John wrote:
> Andrzej,
>
> Andrzej Litwiniuk wrote:
>
>>>So, if I understand you correctly is this allowed ?
>>>
>>>module outer;
>>> ...
>>> module inner;
>>> ...
>>> endmodule
>>>endmodule
>>>
> OK. So I guess the intent must have been that a nested scope SV module
> has the same semantics and purpose as a nested VHDL "block" statement.
>
>>>So we agreed to get rid of "as" and "function". Good.
>>>
>>>Now, the controversy got narrowed down to the order ('cname fname' vs. 'fname cname')
>>>and quotes. Either order is fine for me. Regarding quotes, I disagree with
>>>"less trouble to parse", same trouble or the lack of, but whatever.
>>>I can accept either version.
>>>
>>>Andrzej
>>>
>>>
> Splendid. So I'll update the propsal to show Kevin's syntax with
> allowances
> for interfaces as you described.
>
>-- johnS
> __
>
I've tried putting all the stuff in one document (attached) - it's a
working document
which will change (on feedback), but is intended to drop into the LRM at
some point.
(The BNF may not be accurate.)
Kev.
-- National Semiconductor, Tel: (408) 721 3251 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
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