Subject: Re: [sv-cc] DirectC layer: C array indices mapping for packed arrays
From: Andrzej Litwiniuk (Andrzej.Litwiniuk@synopsys.com)
Date: Mon Feb 03 2003 - 13:13:05 PST
Francoise wrote:
> This is different from the way packed vectors are laid out
> in Verilog simulators.
> If the packed part is [27:1]
> then it is laid out as 1 being the LSB
>
> If the packed part is [1:27] then 27th is the LSB.
I suppose that I was plain wrong for packed arrays.
Let me rephrase what you said. If the packed part is [L:R] then L is
the index of MSB and R is the index of LSB, regardless whether L>R or not.
So the rule for the mapping between SV and C could be as follows:
The normalized indexing for the packed array assumes that LSB has always
the index 0, while MSB has the index n-1, where n is the width.
Will it be ok that way?
Andrzej
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