Subject: [sv-cc] DirectC layer: C array indices mapping question
From: Francoise Martinolle (fm@cadence.com)
Date: Thu Jan 30 2003 - 14:35:48 PST
Andrzej,
I was reading again the DirectC layer proposal you made and trying to
understand
the mapping you propose for SV unpacked array indices.
You say:
"A natural order of elements is assumed for each dimension in the layout of
an unpacked array, i.e. elements with lower indices go first.
In other words, for SV range [l:r], the element with SV index min(l,r) will
have C index 0, and the element with SV index max(l,r) will have C index
abs(l-r). "
If I apply this to the following example:
SV object:
v [0:3] [4:3]
will be laid out as:
a C array: c[4][2]
@c[0][0] => v[0][3] | lowest address
@c[0][1] => v[0][4] |
@c[1][0] => v[1][[3] |
@c[1][1] => v[1][4] V increasing C addresses
etc...
This is different from the way packed vectors are laid out
in Verilog simulators.
If the packed part is [27:1]
then it is laid out as 1 being the LSB
If the packed part is [1:27] then 27th is the LSB.
Is there a particular reason why you choose the proposed mapping?
Why not layout out Verilog like:
v[0][4] @c[0][0]
v[0][3] @c[0][1]
v[1][4] @c[1][0]
v[1][3] @c[1][1]
etc....
This seems to me a more natural way which match the way that people today
interpret the packed
vector layout of bits.
Francoise
'
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