Subject: [sv-cc] FW: [sv-bc] SystemVerilog 3.1 draft 3 available
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Feb 17 2003 - 09:33:27 PST
FYI
-----Original Message-----
From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com]
Sent: Monday, February 17, 2003 9:51 AM
To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: [sv-bc] SystemVerilog 3.1 draft 3 available
All,
Draft 3 of the SystemVerilog 3.1 LRM is now available for download. This
draft contains a new chapter on assertions from the SV-AC committee, plus
updates from the SV-BC and SV-EC committees. Change bars and different
font styles denote all changes from previous editions of the LRM. The
first page has a legend on the different fonts used.
The draft can be downloaded by pointing your web browser to
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft3.pdf
Stu
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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