Subject: [sv-cc] Patent 6,141,630 From Verisity
From: Vassilios.Gerousis@Infineon.Com
Date: Mon Feb 17 2003 - 13:04:47 PST
For the SV-CC members, I would like to technical opinion on the validity of
Patent 6,141,630.
We need to examine it from the Syntax and semantics points of view of what
we are building as
SystemVerilog Part 2 LRM C/API interface. Accellera is not interested in
algorithms, methodology,
or flows. We are building standards for everyone to use (build tools and
also do design and verification).
As of today, Verisity has not provided an further clarification. We need to
provide the Accellera Board with a technical assessment. Any input in this
area is appreciated.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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