Subject: [sv-cc] Fwd: [sv-bc] Cadence Negative Ballot Comment on SystemVerilog 3.1
From: Francoise Martinolle (fm@cadence.com)
Date: Thu Apr 24 2003 - 12:40:05 PDT
Attached is the negative ballot document.
>Subject: [sv-bc] Cadence Negative Ballot Comment on SystemVerilog 3.1
>Date: Thu, 24 Apr 2003 15:30:01 -0400
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>Thread-Topic: Cadence Negative Ballot Comment on SystemVerilog 3.1
>Thread-Index: AcMKl+ThPgQDSJZDQtW49+1ZCUkBAA==
>From: "Jay Lawrence" <lawrence@cadence.com>
>To: <sv-ec@eda.org>, <sv-ac@eda.org>, <sv-bc@eda.org>,
> <accellera_bod@accellera.org>, <sv-cc@eda.org>
>Cc: <Vassilios.Gerousis@Infineon.Com>
>X-Received: By mailgate2.Cadence.COM as MAA25715 at Thu Apr 24 12:38:39 2003
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>
>To all technical subcommittees and the Accellera Board,
>
>Cadence believes that Verilog needs to be extended in order to support
>hardware design and verification within the Verilog environment. We
>have been actively involved in the SystemVerilog Accellera process for
>the last year with representatives on all relevant committees. We
>believe extensions in the areas of data types, constraints and
>randomization, direct interfaces, and assertions are important to the
>productivity of the industry.
>
>Many of the concepts included in SystemVerilog 3.1 move Verilog in this
>direction, but Cadence believes that the draft 5 LRM is not coherent
>and complete enough to be considered by the Board of Directors as a
>proposed Accellera standard. The attached document provides
>detail on the issues Cadence has with the draft 5 LRM. Cadence is
>providing this feedback because we are absolutely committed to
>enhancing Verilog in a manner that will provide the capabilities the
>industry needs, while preserving the users' and vendors' extensive
>investment in IEEE 1364 Verilog.
>
>Jay
>
>
>===================================
>Jay Lawrence
>Senior Architect
>Functional Verification
>Cadence Design Systems, Inc.
>(978) 262-6294
>lawrence@cadence.com
>===================================
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