Subject: RE: [sv-cc] Vote/Poll/Review announcement
From: Swapnajit Mittra (mittra@juno.com)
Date: Fri Oct 17 2003 - 22:01:26 PDT
Francoise,
The acceptance vote on Mentor's donation, as I mentioned
in the ballot, is only to take it as the basis of further
work, NOT FOR ACCEPTING THE TECHNICAL CONTENT (we will do
that on a second vote after the technical discussion
within the team and proposals from various members). This
is mentioned in the operating guidelines:
http://www.eda.org/sv-cc/op-guide.3.1a.html#DonationProposals
Specifically, this vote looks for:
1.Does it address the topic?
2.Is there any missing information?
3.Is there any design, syntactic, and semantic
consistency/conflicts with SystemVerilog 3.1 and
Verilog 1364-2001?
4.Style of the submission consistent with SystemVerilog 3.1
LRM.
Actually, the purpose of the votes are not very different
from what we did last time (3.1).
It seems to me you agree with the objective of the proposal
(the purpose of this vote) but not how to solve it (the
purpose of the yet-to-be-held second vote).
I thought I had clarified this during our meeting but
obviously did not do a good job. You are welcome to re-send
your vote until Monday morning if you want to do so.
And certainly you are (or anybody else is) more than welcome
to send a proposal to the team that solves the disable
problem (issue 1.1).
Regards,
-- Swapnajit Mittra Project VeriPage ::: http://www.angelfire.com/ca/verilog-- Francoise Martinolle <fm@cadence.com> wrote:
-----Original Message----- From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org]On Behalf Of Swapnajit Mittra Sent: Monday, October 13, 2003 11:46 AM To: sv-cc@eda.org Subject: [sv-cc] Vote/Poll/Review announcement
> This is the ballot for the following poll/vote/review. Please > send in your feedback by 10/19/03. > > o Acceptance vote for Mentor's donation > > This is a company ***vote***. Following companies are eligible > for voting. Only one vote per company will be accepted. Please > vote on: 'SV-CC accepts Mentor's donation as the basis for > more discussion and work'. The donation is located at: > http://www.eda.org/sv-cc/hm/1481.html > > - Cadence > - Mentor > - Synopsys > - Motorola
Cadence votes NO to this proposal even though I think that it would be useful to allow this functionality. The main reason I have is that allowing the C code to call a verilog task and suspend the C code execution is very complex to implement and there are some issues with disable statements. Yes I think it would be nice to call a Verilog task but I would rather define it as a callback function so that the C code would not suspend and wait for the Verilog task to finish. Instead, the code would tell the simulator to call it back when that a specific task instance is completed. The disabling issue would also be solved. If people are interested in this idea, I will make a counter proposal to Mentor's proposal.
> > o Poll for Ralph's errata > > > > This is a technical poll on Ralph's errata as listed at: > > http://www.eda.org/sv-cc/hm/1487.html > > > > Following members are eligible for sending comment (Y/N/A). > > - Francoise > - Ralph > - Doug > - Michael > - Joao > - Andrzej > - Ghassan
Approved
> o Review (not vote or poll) for LRM-5 and LRM-17 > > The committee has passed these earlier, but in light of the > later feedbacks from other teams, here is one more round > of review. All are welcome to send technical comments. > http://www.eda.org/sv-cc/hm/1502.html > > --
Approved
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