RE: [sv-cc] vpi_create

I just downloaded the LRM pointed by the accellera web site:
http://www.eda.org/sv/SystemVerilog_3.1a.pdf

and vpi_create has only 3 arguments and not 4.
Bassam, Joao, do you remember if we dropped this from the final spec?

Francoise
        '

At 11:50 AM 5/26/2004 -0700, David W. Smith wrote:
>Have you looked at the 3.1a approved standard as well? Not sure which
>draft you looked at but it has been superceeded by the
>Accellera approved standard at this point.
>
>Regards
>David
>
>David W. Smith
>Synopsys Scientist
>
>Synopsys, Inc.
>Synopsys Technology Park
>2025 NW Cornelius Pass Road
>Hillsboro, OR 97124
>
>Voice: 503.547.6467
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>
>-----Original Message-----
>From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of
>Francoise Martinolle
>Sent: Tuesday, May 25, 2004 12:52 PM
>To: sv-cc@eda.org
>Subject: [sv-cc] vpi_create
>
>I looked at the 3.1A draft and I noticed that vpi_create only takes 3
>arguments.
>Did we drop the capability of specifying an iteration relationship and a
>reference handle to add all the iteration elements to the collection in one
>vpi_create call?
>
>Francoise
> '
Received on Wed May 26 14:56:15 2004