Re: [sv-cc] Errata? Handling DPI parameters of type 'reg'

This is part of a slightly broader problem that will probably need
addressed if Verilog-AMS is merged into SV (which is supposed to be
happening next year):

A reg is actually a composite object, it is the combination of a driver
and a net (or net reference) - writes are to the driver, reads are from
the net (both are usually type 'logic'), and Verilog syntax doesn't allow
any other access. In the case where the reg type is not connected to other
drivers/nets it collapses (semantically) to something that looks like a
simple variable.

Verilog-AMS adds "driver access" functions which allow users to access the
driver values of a net seperately from the resolved values. DPI access
should probably do the same for handling the boundaries to C models.

Kev.

On Wed, 4 Aug 2004, Francoise Martinolle wrote:

> I do agree with your errata request.
> At 04:21 PM 7/27/2004 -0400, Duncan, Ralph wrote:
>
> >Several early DPI users have wanted to pass 'reg' scalars or vectors across
> >the DPI boundary.
> >
> >However, the LRM DPI sections only mention 'logic' scalars and packed
> >arrays as
> >legal 4-state entities for the DPI interface (E.6.4 table and E.6.7).
> >
> >I am told that the group did intend to include 'reg' items. In addition,
> >Dave Rich
> >of SV-BC states that he knows no semantic difference between 'logic' and
> >'reg'
> >as the language now stands.
> >
> >If you do not believe that the 'reg' data type should be essentially
> >treated as
> >being interchangeable with 'logic', please make this known.
> >
> >However, if there is a group consensus that we should accept reg
> >parameters as
> >equivalent to logic parameters, I propose to make this explicit: otherwise
> >the reader
> >must extrapolate our intent or consult type equivalence material separated
> >from the
> >DPI section by hundreds of pages.
> >
> >Three changes might suffice for this:
> >
> >1. E.6.4 table of SV/C type equivalences: replace "logic" with "logic/reg".
> >
> >2. E.6.4 table footnote.
> > The footnote is "Encodings for bit and logic are given in file
> > svdpi.h. Refer to Annex E.9.1.1."
> > (Section E.9.1.1 only discusses scalar encodings).
> > I propose adding the following sentence:
> > "Reg parameters can use the same encodings as logic parameters."
> >
> >3. E.6.7: Sentence preceding Encoding table:
> >
> > Before: "Table E-2 defines the encoding used for a packed logic array
> > represented as svLogicVec32."
> > After: "Table E-2 defines the encoding used for a packed logic or reg
> > array represented as svLogicVec32."
> >
> >Please let me know your opinions on handling the reg type, and on any LRM
> >changes that
> >you believe should or should not be made to support this.
> >
> >Thanks for considering this,
> >Ralph
>
Received on Wed Aug 4 10:29:17 2004