I doubt this interpretation.
Regs have no strengths.
A reg can be written from many sources, but it is not continuously driven, it
simply holds a value, the last one written to it. There is no concept of
contention, etc.
Shalom
Kevin Cameron wrote:
> A reg is actually a composite object, it is the combination of a driver
> and a net (or net reference) - writes are to the driver, reads are from
> the net (both are usually type 'logic'), and Verilog syntax doesn't allow
> any other access. In the case where the reg type is not connected to other
> drivers/nets it collapses (semantically) to something that looks like a
> simple variable.
>
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Reuse Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Thu Aug 5 01:06:39 2004
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