[sv-cc] [Fwd: Call for participation: IEEE 1800 CC - errata committee]

Hi All,

I forgot to CC this email alias on the original message. Sorry
about that. Here is the call for participation which I sent out
to the other aliases of which I am aware. If you think I missed
someone, please let me know.

Please note the meeting information below.

Thanks.

   -Chas

-------- Original Message --------
Subject: Call for participation: IEEE 1800 CC - errata committee
Date: Mon, 13 Sep 2004 13:10:43 -0400
From: Charles Dawson <chas>
Reply-To: chas
To: PTF <ptf@boyd.com>, IEEE1364 <1364@accellera.org>, IEEE1800
<ieee1800@eda.org>, ETF <etf@boyd.com>, btf <btf@boyd.com>
CC: Charles Dawson <chas>

Hi All,

If you have an interest in the C interfaces specifications of the
Verilog IEEE 1364 language and of the SystemVerilog Accellera 3.1a
language,
please join in the IEEE 1800 standardization effort.

There is a sub-committee being formed under the 1800 Errata Task Force to
resolve errata in the SystemVerilog 3.1a specification related to the C
interfaces.

The next meeting will be 9/15/2004 at 9:00am PST. Here is the dial in info:

   US Dial In: 888-635-9997
   International: 763-315-6815
   Participant Code: 2638073

At this meeting we will be trying to find a time that works best for
everyone,
and will begin to parcel out the remaining work before the specification
goes
to ballot.

If you are interested in participating, please send email to
chas@cadence.com
and I will make sure you are on the appropriate email aliases.

Thanks,

   -Chas

-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com