I have posted a concrete proposal as an attached
file for issue 44.
Regards,
Jim Vellenga
--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 
] -----Original Message-----
] From: sv@eda.org [mailto:sv@eda.org] 
] Sent: Wednesday, October 20, 2004 4:37 PM
] Subject: [SystemVerilog Errata 0000044]: var bit vs. 
] vpiVarBitVar in VPI
] 
] 
] The following bug has been ASSIGNED.
] ======================================================================
] http://www.eda.org/svdb/bug_view_page.php?bug_id=0000044
] ======================================================================
] Reported By:                sv-cadence
] Assigned To:                vellenga
] ======================================================================
] Project:                    SystemVerilog Errata
] Bug ID:                     44
] Category:                   SV-CC
] Reproducibility:            always
] Severity:                   feature
] Priority:                   immediate
] Status:                     assigned
] Type:                       Errata
] ======================================================================
] Date Submitted:             07-21-2004 13:36 BST
] Last Modified:              10-20-2004 13:37 BST
] ======================================================================
] Summary:                    var bit vs. vpiVarBitVar in VPI
] Description: 
] The object model diagram for variables in Section 31.10 declares an 
] object named "var bit," but Note 19 of the same section refers to a 
] "var bit var."  Also, in Annex I, sv_vpi_user.h declares a 
] vpiVarBitVar, but not a vpiVarBit.  The rules for interpreting the 
] object model diagrams require that either
] 
] -- the object be named "var bit var," or
] 
] -- the #define name be changed to "vpiVarBit."
] 
] James H. Vellenga
] Cadence Design Systems
] ======================================================================
] 
] Bug History
] Date Modified  Username       Field                    Change 
]              
] ======================================================================
] 07-21-04 13:36 sv-cadence     New Bug                         
]              
] 07-21-04 13:36 sv-cadence     Type                      => 
] Errata          
] 07-22-04 15:18 mittra         Assigned To               => 
] joao            
] 07-22-04 15:18 mittra         Status                   new => 
] assigned     
] 08-06-04 11:28 pieper         Priority                 normal 
] => immediate 
] 10-11-04 14:11 chas           Assigned To              joao 
] =>             
] 10-20-04 13:37 chas           Assigned To               => 
] vellenga        
] ======================================================================
] 
] 
Received on Fri Oct 22 07:23:36 2004
This archive was generated by hypermail 2.1.8 : Fri Oct 22 2004 - 07:24:08 PDT