RE: [sv-cc] 62, 63, and 301: On 31.10 Variables

I am reviewing these changes and I have a question regarding note 4 of 31.10
vpiRange iteration says that it only return the unpacked ranges for an array
var
and the packed ranges for a bit or logic var.
How do we get the packed ranges of an array var? Do we have to iterate on
vpiReg from the
array var and get the variable which represent the vector element of the
array?

Francoise
    '
 

-----Original Message-----
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Jim
Vellenga
Sent: Friday, January 21, 2005 2:24 PM
To: sv-cc@eda.org
Subject: [sv-cc] 62, 63, and 301: On 31.10 Variables

I have looked jointly at the changes made for the following items:

-- 62 (assigned Joao, proposal by Francoise)

-- 63 (assigned to and proposal by Michael)

-- 301 (assigned to and proposal by JimV)

I have verified to my own satisfaction that P1800/D3 has these changes
edited in correctly. But since they are non-trivially related, someone else
should probably look at them. If someone else agrees, then we can move them
to "Closed".

Regards,
Jim V.

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James H. Vellenga 978-262-6381
Engineering Director (FAX) 978-262-6636
Cadence Design Systems, Inc. vellenga@cadence.com
270 Billerica Rd
Chelmsford, MA 01824-4179
"We all work with partial information."
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Received on Fri Jan 21 12:10:22 2005