RE: [sv-cc] Handling trivial issues

Charles,

I reviewed all these items.
There were four of them that I think require more detailed
proposals, since the fixes weren't obvious to me:

 0000470  32.21 Properties should be with defn not ref
 0000460  32.13  need parens at end of routine properties
 0000447  32.5 missing types for properties
 0000439  Annex I - implied properties are really return values

I added bug notes to these items.

Thanks for all this work - you are a veritable one-man wrecking
crew at getting these portions of the LRM into high quality shape.

Regards,
Doug

> -----Original Message-----
> From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
> Behalf Of Charles Dawson
> Sent: Thursday, March 31, 2005 11:04 AM
> To: SV-CC
> Subject: [sv-cc] Handling trivial issues
> 
> Hi All,
> 
> The following items have been identified as trivial, and the fixes
> are obvious.  I have assigned them to Stu, and he has agreed to
> take a look at them prior to our next meeting.  Here is how I would
> like to address them:  At our next meeting, I would like to pass
> them en masse, without going through the trouble of producing formal
> proposals for each of them.  In order to do this everyone (Stu in
> particular) needs to look at them, and agree that the fix is both
> trivial and obvious.  Any issue on this list that someone has a
> doubt about, I will remove, and we will address it individually.
> 
> So, here's the list:
> 
> 0000603  "callee's declared the formals"?
> 0000591  31.11 vpi_get_time() is a void routine - backwards 
> compatibility
> 0000582  31.8.4.2 grammar
> 0000574  31.8.3.2 Typo
> 0000569  31.8.1 typos
> 0000566  31.6 Why is there a double line between 
> vpi_iterate() and vpi_handle()?
> 0000535  32.26 font size of note is inconsistent
> 0000530  Annex E - Examples should use DPI-C label
> 0000527  32.14 grammatical error
> 0000525  32.13 grammatical error
> 0000504  32.53 Missing info from P1364 26.6.42
> 0000503  32.52 'return stmt' should be 'return'
> 0000498  32.50 minor clarification needed here
> 0000491  32.40 Missing null stmt definition
> 0000479  32.26 'refobj' should be 'ref obj'.
> 0000476  32.23 clarify vpiParent label
> 0000471  32.21 typo in note 6
> 0000470  32.21 Properties should be with defn not ref
> 0000466  32.20 'nets' should be 'scope'
> 0000462  32.14 vpiParent label is poorly placed
> 0000461  32.30 indentation for properties is incorrect
> 0000460  32.13  need parens at end of routine properties
> 0000447  32.5 missing types for properties
> 0000446  32.5 incorrect note
> 0000444  32.3 & 32.6 Superfluous note should be removed
> 0000443  32.2 The note needs to go in section 32.7
> 0000439  Annex I - implied properties are really return values
> 0000428  29.4.2 needs better whitespace
> 0000502  32.51 vpiExpr should apply to entire disables class
> 0000500  32.47 Implies all expressions have a vpiName property
> 0000490  32.39 Indexed part select is missing
> 0000488  32.38 vpiMemory should be removed
> 0000477  32.25 missing newer changes from P1364
> 0000457  32.13 LHS of bottom diagram incorrectly drawn
> 0000456  32.13 poorly drawn diagram - regression
> 
> 
>    -Chas
> 
> 
> -- 
> Charles Dawson
> Senior Engineering Manager
> NC-Verilog Team
> Cadence Design Systems, Inc.
> 270 Billerica Road
> Chelmsford, MA  01824
> (978) 262 - 6273
> chas@cadence.com
> 
> 
>