[sv-cc] Index array correspondence: combining two insights

The recent discussion about DPI array index correspondence ultimately
showed we've been 
talking about two different aspects of this issue, perhaps without
realizing it.
 
This note states what those two things are and suggests how we can both
utilize Andrzej's
text and incorporate new text that addresses something that has been
overlooked.
 
1. BACKGROUND
 
Specifying array parameter behavior for a C interface involves two
different things:
 
. ARRAY ASSIGNMENT (element correspondence): that's because array
parameter passing involves
  actual argument to formal argument assignment (at least conceptually).
As an example, for native code
  LRM 5.7 says assignment and element correspondence are
leftmost->leftmost...rightmost->rightmost.
 
. ARRAY STORAGE: because user C code will see the array starting address
as the location 
  of array element[0], we would need to specify storage order to ensure
DPI users' C code is portable
  across simulators.
 
Andrzej's passage must actually describe storage order (import decl
formal->C formal correspondence).
It would be helpful to clarify that this is the case and to add a
statement about array assignment.
 

2. ANDRZEJ'S PASSAGE -- DISCUSSION
 
Why the passage is a reasonable statement of array storage order:  If it
is stating the index correspondence 
between a DPI import declaration formal and the (implicit) user C
formal, then it is essentially describing a 
lo..hi storage order.  This is consonant with the only known LRM
material on storage order, which describes 
lo..hi order for unpacked arrays of Verilog 'memories' (see LRM 22.16).
 
Why it can't be an adequate statement of assignment order (element
correspondence):  If it were prescribing 
the relationship between a SystemVerilog actual argument and the
implicit C formal, it would be ignoring the 
role of the import declaration formal.  This is tantamount to claiming
that import formals with index range 
[hi:lo] and [lo:hi] are semantically equivalent.
 
Thus, Andrzej's text fairly states the array storage order (i.e.,
relation between import decl formal and C formal).
 

3. SUGGESTED SOLUTION
 
Add words that clarify what role Andrzej's text plays and add text that
addresses array element correspondence 
by making DPI element correspondence (actual->import decl formal
assignment) match the native code rules in 5.7. 
 
The current passage:
 
"The natural order of elements for each dimension in the layout of an
unpacked array shall be used,
i.e., elements with lower indices go first. For SystemVerilog range
[L:R], the element with System-
Verilog index min(L,R) has the C index 0 and the element with
SystemVerilog index max(L,R)
has the C index abs(L-R)" (LRM F.6.3).
 
Suggested passage:
 
"The following relation holds for the unpacked array indices of a formal
parameter in a DPI import declaration 
and the indices of the corresponding formal parameter in user C code.
For a SystemVerilog range [L:R] 
that describes import declaration array indices, the import formal array
element with index min(L,R) corresponds to
the C formal array element with index 0 and the import element with
index max(L,R) corresponds to the C element 
with index abs(L-R).  Elements in a SystemVerilog actual argument array
are assigned to a DPI import declaration 
formal parameter array by using the same leftmost to leftmost, rightmost
to rightmost correspondence that 
defines SystemVerilog array assignment (see Sec. 5.7)."
 
An altered version of Mantis item 1343 can incorporate a change along
these lines.
 
Ralph Duncan
Mentor Graphics