[sv-cc] FW: [SystemVerilog P1800 0002005]: Solution for glitch problem in immediate assertions

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Sat Mar 08 2008 - 09:57:01 PST
Hi, SV-CC. 

----------------------------------------------------------------------
 chas - 2008-03-07 13:46
----------------------------------------------------------------------
The SV-CC would like to provide the following feedback on this proposal:

  The #define at the end of the proposal is in the wrong place.  It
should
  be put into the specification using the "replace" "with" formatting so
  that it would have been more clear that the place was incorrect.

Unfortunately, I did not capture where the #define should have been
placed (sorry). 


Can you clarify the problem?

Thanks,
Shalom
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