OK, I have attached a version of the proposal which attempts to address the below concern. However, I had to guess at the right spot for that #define, since as Shalom points out, the comment does not specify! The .doc version contains the change tracking. SV-CC: Can you guys take a look and comment ASAP if this fix is OK, or you had another location in mind for the #define? I would like to fix today, so we can voice vote the fix in tomorrow's SV-AC mtg. Thanks! -----Original Message----- From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On Behalf Of Bresticker, Shalom Sent: Saturday, March 08, 2008 9:57 AM To: SV-CC Cc: sv-ac@server.eda.org Subject: [sv-ac] FW: [SystemVerilog P1800 0002005]: Solution for glitch problem in immediate assertions Hi, SV-CC. ---------------------------------------------------------------------- chas - 2008-03-07 13:46 ---------------------------------------------------------------------- The SV-CC would like to provide the following feedback on this proposal: The #define at the end of the proposal is in the wrong place. It should be put into the specification using the "replace" "with" formatting so that it would have been more clear that the place was incorrect. Unfortunately, I did not capture where the #define should have been placed (sorry). Can you clarify the problem? Thanks, Shalom --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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