In relation to comment [Art45] and [VY46R45]
[FM45]: what is an import typedef declaration:? is it a type name declared in the foreign language that is imported
in SV? If that is a typedef in the foreign language, we do not know the type rules of the foreign language.
I do not understand how this can be used and work when imported in SV.
In relation to comment [Art51] and [VY52R51]:
SystemVerilog only allowed covariance for function return arguments, it does not specify
covariance of the output arguments. Are we allowing more here? Should'nt this also depends if the foreign
language permits covariance?
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