Foundation Series software is a complete ready-to-use set of tightly integrated, easy-to-use tools that give you the highest performance and the highest density FPGA and CPLD implementations, independent of your expertise or the complexity of your design.  You are assured of success on each and every design because the Foundation Series gives you the advanced tools and technology you need, and you are backed by our well staffed, highly skilled, software applications support team.  

HDL Design Made Simple  
The Foundation Series incorporates state-of-the-art HDL design tools including support for both VHDL and Verilog.  Graphical entry capabilities are provided in a complete, mixed level design environment, featuring: 

• HDL Editor - Provides extensive color coded editing and searching capabilities with integrated syntax checking
• Language Assistant - Speeds design entry by managing the Xilinx supplied library of commonly used language constructs and logic modules, as well as user created libraries
• State Editor - Enables fast, intuitive, graphical entry of both simple and complex state machines.

A Comprehensive Set of Implementation Tools 
The Foundation Series includes a full set of implementation tools, seamlessly 
 integrated to help you create the most efficient and compact deigns that operate at the highest possible speed. These features include: 

• Timing Driven Place and Route - Allows you to specify your timing requirements for critical paths. This feature often gives 30-40% performance improvements when speed is critical; you no longer need to manually fine-tune your design.
• Static Timing Analysis - Shortens your design process by providing an evaluation of your timing at various point in the implementation process, allowing you to make changes immediately.
• Flow Engine - Automates and simplifies the implementation process.  Using a simple graphical interface, you can monitor and control all aspects of your design implementation.
• Simulation - Provides design verification before and after implementation, thus reducing the number of design iterations required to meet design specifications. New in Foundation release 1.4 is the ability to simulate up to 250K gates.
• Incremental Design Capability - Reduces your overall design cycle by allowing you to re-use previous iterations of your design.  This is very helpful for evaluating design alterations.

Features		Foundation Series Part Numbers
		FND-BAS		FND-STD		FND-BSX		FND-EXP
HDL Design Tools  (VHDL and Verilog synthesis)
Synopsys FPGA Express Synthesis
Push-Button Synthesis
Timing Constraint Entry
Static Timing Analysis
Schematic Editor
Simulator (Timing)
ABEL Synthesis Tools
Implementation Tools  EDIF, VHDL, (VITAL), and Verilog back annotation, LogiBLOX, Module Generator  CPLD Devices (XC9500 Family)
FPGA (Low Density/High Volume Devices)    XC3x00A/L, XC4000E/X (Up to XC4010E/X),  XC5000 (Up to SC5210), Spartan Devices (All)
FPGA (Unlimited Device Support)

Xilinx implementation technology has pioneered the use of timing driven design; a feature developed to automatically place and route your design based on your timing requirements.  New in implementation technology is the ability to balance the need for design performance and place and route tool runtime.  This feature saves you time by allowing you to decide how hard the place and route engine should work on driving the performance of your design.  Your design will be optimized based on your timing requirements and a level of effort you choose.  When a minimal effort is requested, runtimes will be dramatically reduced while achieving your defined timing requirements.  When a Maximum effort is requested, a higher level of performance can be achieved.  

All of the advanced technology within the Foundation Series works seamlessly together. For example, you can embed VHDL and Verilog components into a top level schematic, and then simulate the entire design.  And, though you have complete control of every aspect of your design entry and implementation process, you also have access to push-button design flows that simplify the implementation of most designs. 

Foundation Standard System Implementation Flow:  

Full screen view of implementation flow diagram printable in landscape mode.  Text description of the Foundation Standard System implementation flow.

The Foundation Express System incorporates advanced synthesis technology from Synopsys into the Foundation Standard System providing push-button and constraint driven synthesis for VHDL and Verilog. 

Foundation Express System Implementation Flow: 

Full screen view of implementation flow diagram printable in landscape mode.  Text description of the Foundation Express System implementation flow.

Foundation F1.4 Standard and Express systems feature Xilinx's new M1 design implementation technology which delivers industry-leading device performance and utilization. 

Summary 
The Foundation Series supports the full line of Xilinx FPGAs and CPLDs including our XC3000, XC4000E/X, XC5000, XC9500, and Spartan families. Also included are synthesis tools for ABEL; interfaces to EDIF, VHDL, and Verilog; and the most efficient HDL design tools in the industry. The table above lists the Foundation Series features. 

More Information 
 

Compare Foundation's Superior Synthesis!  Fastest Clock Rates, Shortest Runtimes!  Promotional Pricing  Evaluation Kit Foundation Ships 10,000th System  System Level Design for Foundation Customers  Online Presentations  Online Licensing  Hard Copy Literature Request

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