| Title |
Size
|
Summary
|
Family
|
Design
|
 Using the Virtex Block SelectRAM+ Features v1.4 (12/18/00) |
95 KB
|
|
Virtex
|
|
170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature v1.5 (02/13/01)  |
50 KB
|
|
Virtex
|
PC
UNIX |
| Using the Virtex Delay-Locked Loop v2.3 (09/20/00) |
90 KB
|
|
Virtex
|
|
| Using the Virtex SelectI/O Resource v2.4 (04/17/00) |
230 KB
|
|
Virtex
|
|
| Virtex Synthesizable High Performance SDRAM Controller v3.1 (02/01/00) |
105 KB
|
|
Virtex
|
PC:VHDL
PC:Verilog
UNIX:VHDL
UNIX:Verilog |
| Virtex I/V Curves for Various Output Options |
20 KB
|
|
Virtex
|
|
| Synthesizable 143 MHz ZBT SRAMInterface v2.0 (01/00) |
90 KB
|
|
Virtex
|
PC
UNIX |
| Configuring Virtex FPGAs from Parallel EPROMs with a CPLD |
90 KB
|
|
Virtex
XC9500
|
PC |
| Virtex Configuration and Readback v2.2 (09/21/00) |
240 KB
|
|
Virtex
|
|
| Configuration and Readback of Virtex FPGAs Using (JTAG) Boundary-Scan v1.2 (2/00) |
88 KB
|
|
Virtex/-E
|
|
| In-System Programming Times for XC9500XL |
10 KB
|
|
XC9500XL
|
|
| Designing CPLD Multi-voltage Systems v1.3 (03/00) |
65 KB
|
|
CPLD
|
|
| I/V Curves for Various Device Families |
20 KB
|
|
All
|
|
| Virtex Series Configuration Architecture User Guide v1.4 (08/03/00) |
245 KB
|
|
Virtex
|
|
| Virtex Power Estimator User Guide v1.1 (2/00) |
90 KB
|
|
Virtex
|
worksheet |
| Status and Control Semaphore Registers Using Partial Reconfiguration |
180 KB
|
|
Virtex
|
PC |
| Virtex Synthesizable Delta-Sigma DAC |
60 KB |
|
Virtex
|
|
| Virtex Analog to Digital Converter |
50 KB |
|
Virtex
|
|
| Board Routability Guidelines with Xilinx Fine-Pitch BGA Packages v1.0 (07/26/00) |
1,800 KB
|
|
Virtex
|
|
| Powering Virtex FPGAs v1.4 (02/06/01) |
70 KB
|
|
Virtex
|
|
| XC1700 and XC18V00 Design Migration Considerations |
60 KB
|
|
XC1700E/L, XC1800
|
|
| Using Xilinx and Synplify for Incremental Designing (ECO) |
40 KB
|
|
FPGA
|
PC
UNIX |
| Using Xilinx and Exemplar for Incremental Designing (ECO) |
70 KB
|
|
FPGA
|
PC
UNIX |
| TAU/BLAST Support in 2.1i |
20 KB
|
|
FPGA
|
|
| Getting Started With the MultiLINX Cable v1.2 (04/20/00) |
180 KB
|
|
FPGA
|
|
| MP3 NG: A Next Generation Consumer Platform v1.0 (01/00) |
360 KB
|
|
Spartan-II
|
|
| Implementing an ISDN PCMCIA Modem Using Spartan Devices v1.0 (7/99) |
|
|
Spartan
|
|
| Implementing an ADSL to USB Interface Using Spartan Devices v1.0 (3/99) |
|
|
Spartan
|
|
| The Design of a Video Capture Board Using the Spartan Series v1.0 (3/99) |
|
|
Spartan
|
|
| Using Block SelectRAM+ Memory in Spartan-II FPGAs v1.1 (12/11/00) |
100 KB
|
|
Spartan-II
|
|
| Using Delay-Locked Loops in Spartan-II FPGAs v1.0 (01/00) |
120 KB
|
|
Spartan-II
|
PC
UNIX |
| High Speed FIFOs In Spartan-II FPGAs v1.0 (01/00) |
50 KB
|
|
Spartan-II
|
PC
UNIX |
| Spartan-II FPGA Family Configuration and Readback v1.0 (01/00) |
400 KB
|
|
Spartan-II
|
|
| Spartan-Family I/V Curves for Various Output Options v1.0 (01/00) |
30 KB
|
|
Spartan-II
|
|
| Configuring Spartan-II FPGAs from Parallel EPROMs v1.0 (01/00) |
100 KB
|
|
Spartan-II
|
|
| Using SelectI/O Interfaces in Spartan-II FPGAs v1.0 (01/00) |
300 KB
|
|
Spartan-II
|
|
| SEU Mitigation Design Techniques for the XQR4000XL v1.0 (03/15/00) |
105 KB
|
|
FPGA
|
|
| Interfacing a Virtex-E Device to a MIPS Processor v1.0 (12/15/00) |
100 KB
|
|
Virtex
|
|
| Interfacing a Virtex-E Device to a Pentium Processor v1.0 (12/15/00) |
70 KB
|
|
Virtex
|
|
| Virtex Synthesizable 1.6 Gbytes/s DDR SDRAM Controller v2.3 (03/21/00) |
105 KB
|
|
Virtex
|
|
| An Overview of Multiple CAM Designs in Virtex Devices |
40 KB
|
|
Virtex
|
|
| Content Addressable Memory (CAM) in ATM Applications v1.2 (01/06/01) |
140 KB
|
|
Virtex, Virtex-II
|
PC |
| Designing Flexible, Fast CAMs with Virtex Slices |
100 KB
|
|
Virtex
|
PC
UNIX
|
| Using Block RAM for High-Performance Read/Write CAMs v1.2 (05/02/00) |
100 KB
|
|
Virtex
|
|
| Data-Width Conversion FIFOs Using the Virtex Block SelectRAM Memory v1.3 (08/10/00) |
50 KB
|
|
Virtex
|
|
| An Inverse Discrete Cosine Transform (IDCT) Implementation in Virtex Devices for MPEG Video Applications v1.1 (01/00) |
40 KB
|
|
Virtex
|
design |
| Linear Feedback Shift Registers in Virtex Devices v1.2 (01/09/01) |
85 KB
|
|
Virtex, Virtex-II
|
|
| PN Generators Using the SRL Macro v1.1 (01/09/01) |
120 KB
|
|
Virtex, Virtex-II, Spartan-II
|
|
| CDMA Matched Filter Implementation in Virtex Devices v1.1 (01/10/01) |
170 KB
|
|
Virtex, Virtex-II, Spartan-II
|
|
| 8-Bit Microcontroller for Virtex Devices v1.0 (09/25/00) |
380 KB
|
|
Spartan-II
|
|
| Design Tips for HDL Implementation of Arithmetic Functions v1.0 (06/28/00) |
78KB
|
XAPP215 |
Virtex
|
|
| Correcting Single-Event Upsets Through Virtex Partial Configuration v1.0 (06/01/00) |
110 KB
|
|
Virtex
|
|
| Gold Code Generators in Virtex Devices v1.1 (01/10/01) |
125 KB
|
|
Virtex, Virtex-II, Spartan-II
|
|
| Transposed Form FIR Filters v1.1 (01/10/01) |
150 KB
|
|
Virtex, Virtex-II
|
|
| LFSRs as Functional Blocks in Wireless Applications v1.1 (01/11/01) |
135 KB
|
|
Virtex, Virtex-II, Spartan-II
|
|
| 200 MHz UART with Internal 16-Byte Buffer v1.0 (01/31/01) |
150 KB
|
|
Virtex, Virtex-II, Spartan-II
|
|
| Data Recovery in Virtex and Virtex-II Devices v1.1 (01/10/01) |
60 KB
|
|
Virtex, Virtex-II
|
|
| The LVDS I/O Standard |
70 KB
|
|
Virtex-E
|
|
| Multi-Drop LVDS with Virtex-E FPGAs |
85 KB
|
|
Virtex-E
|
|
| Virtex-E LVDS Drivers & Receivers: Interface Guidelines v1.0 (11/99) |
85 KB
|
|
Virtex-E
|
|
| Multi-Channel 622 Mb/s LVDS Data Transfer for Virtex-E Devices v1.2 (01/06/01) |
260 KB
|
|
Virtex-E
|
|
| Virtex SelectLink Communications Channel v1.0 (12/99) |
25 KB
|
|
Virtex-E
|
|
| Virtex Package Compatibility Guide v1.3 (06/20/00) |
40 KB
|
|
Virtex
|
|
| LVDS System Data Framing v1.0 (12/18/00) |
80 KB
|
|
Virtex-E
|
|
| High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices v1.0 (03/14/00) |
80 KB
|
|
Virtex-EM
|
|
| Virtex-EM FIR Filter for Video Applications v1.0 (03/14/00) |
60 KB
|
|
Virtex-EM
|
|
| Interfacing to Lara Networks Search Engine Using Virtex Devices v1.0 (06/08/00) |
80 KB
|
|
Virtex-EM
|
|
| PowerPC 60X Bus Interface to a Virtex-E
Device v1.0 (12/15/00) |
165 KB
|
|
Virtex-E
|
|
| Synthesizable 266 MBits/s DDR SDRAM
Controller v1.0 (01/12/01) |
155 KB
|
|
Virtex-II
|
|
| The Virtex-II SiberBridge v1.0 (01/12/01) |
120 KB
|
|
Virtex-II
|
|
| FIFOs Using Virtex-II Shift Registers v1.0 (01/15/01) |
50 KB
|
|
Virtex-II
|
|
| FIFOs Using Virtex-II Block RAM v1.1 (02/13/01) |
60 KB
|
|
Virtex-II
|
|
| Data-Width Conversion FIFOs Using the
Virtex-II Block RAM Memory v1.0 (01/10/01) |
80 KB
|
|
Virtex-II
|
|
| Quad DataRate (QDR) SRAM Interface for
Virtex-II Devices v1.0 (01/15/01) |
80 KB
|
|
Virtex-II
|
|
| Parity Generation and Validation
in Virtex-II Devices v1.0 (01/15/01) |
45 KB
|
|
Virtex-II
|
|
