To assign I/O in the ProASIC3E family:
From Designer's Tools menu, choose Device Selection. Select a die, package, speed, and die voltage, and click Next.
In the Device Selection Wizard-Variations dialog box, from the Default I/O Standard drop-down list, select the default I/O standard for all generic I/O macros. This action sets the same VCCI for each bank. You cannot choose LVDS or LVPECL as the default I/O standard. If your design has only one single-ended I/O and one VCCI requirement, go to step 8. Otherwise, in the next step you will specify the I/O standards for each I/O bank.
Start either ChipPlanner or PinEditor.
From the Edit menu, choose I/O Bank Settings.
In the I/O Bank Settings dialog box, choose an I/O standard for each I/O bank.
In ChipPlanner or PinEditor, assign VREF pins, if the standard requires VREF voltage. See Assigning VREF pins. In ProASIC3E, you can use any I/O as a VREF pin. The default VREFs setting may create more VREF pins than needed and may result in a loss of usable user I/Os. If that happens, you can choose the custom VREF setting. You must create enough VREF pins to allow a legal placement of the compatible user-voltage-referenced I/O macros. After you assign the VREF pins, right-click a VREF pin and choose Highlight VREF Range to see how many I/Os are covered by this pin.
After assigning VREF pins, from the Tools menu, choose DRC to check the I/O voltage assignment and to generate an I/O bank report. The I/O voltage Usage section in this report shows whether you have enough I/Os available for each voltage. Any infeasible voltage requirements appear as an asterisk (*) in the I/O voltage Usage report. If asterisks appear in your report, you should resolve the problem before continuing.
Once you have completed the I/O bank assignments, you can assign I/O macros to individual pad locations using either the MultiView Navigator or a PDC file.
Note: Choosing Commit from the File menu also performs the DRC check.