Design requirements are often imported using clock, input delay, and output delay constraints. By default, most static timing analyzers assume that all paths are sensitizable. They also assume that the design is operating in a single-cycle mode (that is, only one clock cycle is allowed for the data to transfer from one sequential stage to another).
If any paths in your design exhibit a different behavior, you must use timing exceptions to overwrite the default behavior. Timing exceptions include:
Setting a false path constraint to identify non sensitizable paths that should not be included in the analysis or the optimization flow.
Setting a maximum delay constraint on specific paths to relax or tighten the original clock constraint requirement on them.
Setting a multicycle constraint to specify paths that by design will take more than one cycle to exchange data between sequential components.
SmartTime supports all these exceptions.