/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)addr_reg.v
***
*** Description:
*** Implements the afx address reg capture.
***
****************************************************************************
****************************************************************************/
// changed to have no muxes etc. in front of ab, s_reply, lo_addr, aen
// to improve timing.
module addr_reg
(
clock,
lo_addr,
aen,
ab,
s_reply,
reset,
p_reply,
pa_hold,
bm_hold,
afx_write,
load_addr_fifo,
load_bm_fifo,
load_cmd_fifo,
afx_slave_drive_db,
low_word_en,
boot_mode,
boot_mode_hold,
any_hi_word_en
);
// Port declarations
input clock
;
input lo_addr
;
input aen
;
input [14:0] ab
;
input [1:0] s_reply
;
input reset
;
input [1:0] p_reply
;
output [27:3] pa_hold
; // latched physical address
output [3:0] bm_hold
; // latched byte masks
output afx_write
;
output load_cmd_fifo
;
output load_addr_fifo
;
output load_bm_fifo
;
output afx_slave_drive_db
;
// add to allow both data and instruction access
// during boot mode.
input boot_mode
;
output boot_mode_hold
;
output low_word_en
;
output any_hi_word_en
;
wire low_word_en;
wire any_hi_word_en;
reg [13:0] hi_addr_hold
;
reg [13:0] hi_addr_hold_d1
;
reg [14:0] lo_addr_hold
;
reg [1:0] s_reply_reg
;
wire load_addr_fifo,load_bm_fifo;
reg falcon_en
;
reg falcon_en_d1
;
reg afx_slave_drive
;
wire load_cmd_fifo ;
reg aen_hold
;
reg lo_addr_reg
;
reg boot_mode_hold;
// make sure afx write is only on for the cycles in which the command and
// data fifos are loaded
wire afx_write = falcon_en_d1 & (s_reply_reg == 2'b10) & aen_hold & lo_addr_reg;
wire afx_slave_drive_db = (~reset & (((s_reply_reg== 2'h3)
& falcon_en_d1 & aen_hold & lo_addr_reg)
| ~(p_reply== 2'h3) & afx_slave_drive));
// allow the afx slave to drive the two cycles after the read request is
// received and continue driving until the p_reply is sent
always @(posedge clock)
begin
afx_slave_drive <= #1 (~reset & (((s_reply_reg== 2'h3) & falcon_en_d1
& aen_hold & lo_addr_reg) | ~(p_reply== 2'h3) & afx_slave_drive));
end
always @(posedge clock)
begin
hi_addr_hold <= #1 ab[14:1];
falcon_en <= #1 ab[0];
lo_addr_hold <= #1 ab;
s_reply_reg <= #1 s_reply;
aen_hold <= #1 aen;
lo_addr_reg <= #1 lo_addr;
boot_mode_hold <= #1 (boot_mode & aen);
if (aen_hold && ~lo_addr_reg)
begin
hi_addr_hold_d1 <= #1 hi_addr_hold;
falcon_en_d1 <= falcon_en;
end
end
assign #1 load_addr_fifo = (aen_hold & lo_addr_reg & falcon_en_d1);
assign #1 load_bm_fifo = (aen_hold & lo_addr_reg & falcon_en_d1);
assign #1 load_cmd_fifo = (aen_hold & lo_addr_reg & falcon_en_d1);
// only the command fifo is examined on output, so the address and
// byte marks can be loaded the cycle after the address is received.
wire [27:3] pa_hold = {hi_addr_hold_d1, lo_addr_hold[10:0]} ;
wire [3:0] bm_hold = lo_addr_hold[14:11] ;
assign low_word_en = (bm_hold == 4'h9);
assign any_hi_word_en = (bm_hold[3:2] == 2'b01) | (bm_hold[3:2] == 2'b11) &
~bm_hold[0] | (bm_hold == 4'hd);
endmodule
This page: |
Created: | Thu Aug 19 12:03:12 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afx_slave/rtl/addr_reg.v
|