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H |
Connects up to: | Mflipflop_rh:dff:enable_l |
Connects up to: | Mflipflop_sh:dff:enable_l , Mflipflop:dff:enable_l |
Connects up to: | Mflipflop_srh:dff:enable_l , MflipflopR:dff:enable_l , rsflop:dff:global_reset , rsflop:dff:reset , rsflop:dff:hold |
Connects down to: | JAND8B:i:A8 |
Connects up to: | Exception:zxd:BM |
Connects down to: | JNAND8C:i:A8 |
Connects down to: | JNAND8C:i:A8 |
Connects up to: | CheckOverflow:g10:FracResult |
Connects down to: | AG2222A:i:D2 |
Connects down to: | AG2222A:i:D2 |
Connects down to: | JNOR8C:u0:A8 |
Connects up to: | Exception:g10:BM |
Connects down to: | JNOR8C:u0:A8 |
Connects down to: | JOR8B:i:A8 |
Connects up to: | ShiftRightCtl:g80:Stky8 |
Connects down to: | Mir_control:ir_control:half_store_d |
Connects up to: | Miuchip:decode:half_store_d |
Connects up to: | Mdecode:ir_control:half_store_d |
Connects down to: | Mdecode:decode:half_store_d , Mregfile:regfile:half_store_d |
Connects up to: | Miuchip:regfile:half_store_d |
Connects down to: | Mflipflop_1:half_st_e_reg_1:din |
Connects down to: | Mflipflop_1:half_st_e_reg_1:out |
Connects down to: | Mflipflop_1:phelp_ctr5_reg_1:din |
Connects up to: | Mdecode:alu_control:help_ctr |
Connects up to: | Mdecode:data_byp1_2:help_ctr |
Connects up to: | Mdecode:data_byp2:help_ctr |
Connects down to: | Mflipflop_6:help_ctr_reg_6:out |
Connects up to: | Mdecode:pipec_help_ilock:help_ctr |
Connects up to: | Mdecode:special_reg_control:help_ctr |
Connects up to: | Mdecode:special_reg_control:help_ctr |
Connects down to: | ME_TIEOFF:toff:VDD , ME_INVA:g0:a , ME_INVA:g1:a , ME_INVA:g2:a , ME_INVA:g3:a , ME_INVA:g4:a , ME_INVA:g6:a , ME_INVA:g7:a , ME_INVA:g8:a |
Connects up to: | Mdecode:alu_control:hidiv_in_d |
Connects down to: | Mpipec_im_id:pipec_im_id:hidiv_in_d , Malu_control:alu_control:hidiv_in_d |
Connects up to: | Mdecode:pipec_im_id:hidiv_in_d |
Connects down to: | Mflipflop_2:result_high2_reg_2:din |
Connects up to: | Mdecode:alu_control:high_2_1 |
Connects down to: | Malu_control:alu_control:high_2_1 |
Connects up to: | Miuchip:decode:high_2_1 |
Connects up to: | Miuchip:exec:high_2_1 |
Connects down to: | Mdecode:decode:high_2_1 , Mexec:exec:high_2_1 |
Connects up to: | Mdecode:alu_control:himul_in_d |
Connects down to: | Mpipec_im_id:pipec_im_id:himul_in_d , Malu_control:alu_control:himul_in_d |
Connects up to: | Mdecode:pipec_im_id:himul_in_d |
Connects up to: | cam:tag00:hit , cam:tag01:hit , cam:tag02:hit , cam:tag03:hit , cam:tag04:hit , cam:tag05:hit , cam:tag06:hit , cam:tag07:hit , cam:tag08:hit , cam:tag09:hit , cam:tag10:hit , cam:tag11:hit , cam:tag12:hit , cam:tag13:hit , cam:tag14:hit , cam:tag15:hit , cam:tag16:hit , cam:tag17:hit , cam:tag18:hit , cam:tag19:hit , cam:tag20:hit , cam:tag21:hit , cam:tag22:hit , cam:tag23:hit , cam:tag24:hit , cam:tag25:hit , cam:tag26:hit , cam:tag27:hit , cam:tag28:hit , cam:tag29:hit , cam:tag30:hit , cam:tag31:hit |
Connects up to: | iocam:tag00:hit , iocam:tag01:hit , iocam:tag02:hit , iocam:tag03:hit , iocam:tag04:hit , iocam:tag05:hit , iocam:tag06:hit , iocam:tag07:hit , iocam:tag08:hit , iocam:tag09:hit , iocam:tag10:hit , iocam:tag11:hit , iocam:tag12:hit , iocam:tag13:hit , iocam:tag14:hit , iocam:tag15:hit |
Connects down to: | Mflipflop_10:GReg_10_10:enable_l |
Connects down to: | Mflipflop_11:GReg_11_11:enable_l |
Connects down to: | Mflipflop_12:GReg_12_12:enable_l |
Connects up to: | rl_col_row_addr:ffh_row_mm_reg:gaddr_hld |
Connects down to: | Mflipflop_2:GReg_2_2:enable_l |
Connects up to: | rl_col_row_addr:ffh_mm_mem_dbg_n:mm_issue_req , rl_col_row_addr:ffh_col_mm_hi_in:hld_mm_pa |
Connects down to: | Mflipflop_3:GReg_3_3:enable_l |
Connects up to: | rl_col_row_addr:ffh_gaddr_27_25:gaddr_hld , rl_mcb_sm:ffh_srcreg54:cyc_hld , rl_mcb_sm:ffh_srcreg54_2:cyc_hld |
Connects down to: | Mflipflop_4:GReg_4_4:enable_l |
Connects up to: | rl_col_row_addr:ffh_bm:odat_hld , rl_mcb_sm:ffh_srcreg30:cyc_hld_read , rl_mcb_sm:ffh_srcreg30_2:cyc_hld_read |
Connects down to: | Mflipflop_5:GReg_5_5:enable_l |
Connects down to: | Mflipflop_6:GReg_6_6:enable_l |
Connects down to: | Mflipflop_7:GReg_7_7:enable_l |
Connects up to: | rl_reqtimer:ffh_reqtim:hld |
Connects down to: | Mflipflop_8:GReg_8_8:enable_l |
Connects down to: | Mflipflop_9:GReg_9_9:enable_l |
Connects up to: | rl_col_row_addr:ffh_gaddr_11_3:gaddr_hld |
Connects down to: | GReg7:ffh_reqtim:hld |
Connects down to: | MflipflopR_31:afar_31:enable_l |
Connects up to: | mmu:MMU_dp:hld_afar |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_afar , dp_mmu:MMU_dp:hld_afar |
Connects down to: | rl_mmu_regs:mmu_regs:hld_afar |
Connects up to: | mmu:MMU_cntl:hld_afar |
Connects up to: | m_mmu_cntl:mmu_regs:hld_afar |
Connects down to: | MflipflopR_1:afx_qlvl_ff_1:enable_l |
Connects down to: | Mflipflop_h_32:beis_reg:enable_l , Mflipflop_h_32:bois_reg:enable_l |
Connects down to: | Mpc_cntl:pc_cntl:hld_backup |
Connects up to: | Miuchip:decode:hld_backup |
Connects down to: | Mqueue:queue:hld_backup , Mdecode:decode:hld_backup |
Connects up to: | Mdecode:pc_cntl:hld_backup |
Connects up to: | Miuchip:queue:hld_backup |
Connects down to: | Mflipflop_1:hld_backup_almost_reg_1:out |
Connects down to: | Mflipflop_32:ic_even_bu_reg_32:enable_l , Mflipflop_32:ic_odd_bu_reg_32:enable_l , Mflipflop_11:ic_iexc_bu_11:enable_l |
Connects down to: | Mpc_cntl:pc_cntl:hld_car_mar |
Connects up to: | Miuchip:decode:hld_car_mar |
Connects down to: | Mpc:pc:hld_car_mar , Mdecode:decode:hld_car_mar |
Connects up to: | Miuchip:pc:hld_car_mar |
Connects down to: | Mflipflop_1:hld_llc_reg_1:din |
Connects up to: | Mdecode:pc_cntl:hld_car_mar |
Connects down to: | Mflipflop_30:car_register_30:enable_l |
Connects down to: | MflipflopR_18:ctpr_18:enable_l |
Connects up to: | mmu:MMU_dp:hld_ctpr |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_ctpr , dp_mmu:MMU_dp:hld_ctpr |
Connects down to: | rl_va_mux:va_muxl:hld_ctpr |
Connects up to: | mmu:MMU_cntl:hld_ctpr |
Connects up to: | m_mmu_cntl:va_muxl:hld_ctpr |
Connects down to: | MflipflopR_8:tlb_cxr_8:enable_l |
Connects up to: | mmu:MMU_dp:hld_cxr |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_cxr , dp_mmu:MMU_dp:hld_cxr |
Connects down to: | rl_va_mux:va_muxl:hld_cxr |
Connects up to: | mmu:MMU_cntl:hld_cxr |
Connects up to: | m_mmu_cntl:va_muxl:hld_cxr |
Connects down to: | Mpc_cntl:pc_cntl:hld_dir2 |
Connects up to: | Miuchip:decode:hld_dir2 |
Connects down to: | Mqueue:queue:hld_dir2 , Mdecode:decode:hld_dir2 |
Connects up to: | Mdecode:pc_cntl:hld_dir2 |
Connects up to: | Miuchip:queue:hld_dir2 |
Connects down to: | Mflipflop_h_32:oops_reg:enable_l , Mflipflop_h_32:oops_f_reg:enable_l |
Connects down to: | Mflipflop_10:backup_dir_reg_10:enable_l , Mflipflop_9:backup_biexc_reg_9:enable_l |
Connects down to: | Mflipflop_30:p_fold_aa_reg_30:enable_l , Mflipflop_32:backup_dir_reg_32:enable_l , Mflipflop_11:backup_iexc_reg_11:enable_l |
Connects down to: | fp_fpc:fpfpc:hld_dirreg |
Connects up to: | ssparc_core:ssparc_fpu:hld_dirreg |
Connects down to: | fp_qst:fpqst:hld_ir_d |
Connects up to: | fpufpc:fpfpc:hld_dirreg |
Connects down to: | Mflipflop_h_32:oops_reg:din , Mflipflop_h_32:oops_f_reg:din |
Connects down to: | Mir_control:ir_control:hld_dirreg , Minterface:interface:hld_dirreg , Mir:ir:hld_dirreg |
Connects up to: | Miuchip:decode:hld_dirreg |
Connects up to: | Mdecode:interface:hld_dirreg |
Connects up to: | Mdecode:ir:hld_dirreg |
Connects up to: | Mdecode:ir_control:hld_dirreg |
Connects down to: | Miuchip:iuchip:hld_dirreg |
Connects up to: | ssparc_core:iu:hld_dirreg |
Connects down to: | Mqueue:queue:hld_dirreg , Mdecode:decode:hld_dirreg |
Connects up to: | Miu:iuchip:hld_dirreg |
Connects up to: | Miuchip:queue:hld_dirreg |
Connects down to: | Mflipflop_5:brs1_decm_reg_5:enable_l , Mflipflop_5:brs2_decm_reg_5:enable_l |
Connects up to: | Miuchip:regfile:hld_dirreg_rf |
Connects down to: | Miu:iu:hld_dirreg , fpufpc:ssparc_fpu:hld_dirreg |
Connects down to: | Mflipflop_h_32:dis_reg:enable_l |
Connects down to: | Mflipflop_32:dummy_dir_reg_32:enable_l |
Connects down to: | Mir_control:ir_control:hld_dirreg_rf |
Connects up to: | Miuchip:decode:hld_dirreg_rf |
Connects up to: | Mdecode:ir_control:hld_dirreg_rf |
Connects down to: | Mdecode:decode:hld_dirreg_rf , Mregfile:regfile:hld_dirreg |
Connects down to: | MflipflopR_31:dpar_reg_31:enable_l |
Connects up to: | mmu:MMU_dp:hld_dpar |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_dpar , dp_mmu:MMU_dp:hld_dpar |
Connects down to: | rl_par_cntl:par_cntl:dpar_valid , rl_mmu_regs:mmu_regs:dpar_valid |
Connects up to: | mmu:MMU_cntl:hld_dpar |
Connects down to: | Mpc_control:pc_control:hld_dpc |
Connects up to: | Miuchip:decode:hld_dpc |
Connects down to: | Mpc:pc:hld_dpc , Mdecode:decode:hld_dpc |
Connects up to: | Miuchip:pc:hld_dpc |
Connects up to: | Mdecode:pc_control:hld_dpc |
Connects down to: | Mflipflop_1:dsign_bit2_reg_1:enable_l |
Connects down to: | Mpc_control:pc_control:hld_dum_dpc |
Connects up to: | Miuchip:decode:hld_dum_dpc |
Connects down to: | Mqueue:queue:hld_dum_dpc , Mdecode:decode:hld_dum_dpc |
Connects up to: | Mdecode:pc_control:hld_dum_dpc |
Connects up to: | Miuchip:queue:hld_dum_dpc |
Connects down to: | Mflipflop_30:dummy_dpc_reg_30:enable_l |
Connects down to: | Mflipflop_9:fill_adr_hi_reg_9:enable_l |
Connects down to: | MflipflopR_17:ibar_17:enable_l |
Connects up to: | mmu:MMU_dp:hld_ibar |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_ibar , dp_mmu:MMU_dp:hld_ibar |
Connects down to: | rl_mmu_regs:mmu_regs:hld_ibar |
Connects up to: | mmu:MMU_cntl:hld_ibar |
Connects up to: | m_mmu_cntl:mmu_regs:hld_ibar |
Connects down to: | MflipflopR_4:io_cr_4:enable_l |
Connects down to: | MflipflopR_31:ipar_reg_31:enable_l |
Connects up to: | mmu:MMU_dp:hld_ipar |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_ipar , dp_mmu:MMU_dp:hld_ipar |
Connects down to: | rl_par_cntl:par_cntl:ipar_valid , rl_mmu_regs:mmu_regs:ipar_valid |
Connects up to: | mmu:MMU_cntl:hld_ipar |
Connects down to: | ME_OR2_B:iu_hold_gate_1:b , ME_OR2_B:iu_hold_gate_2:b , ME_OR2_B:iu_hold_gate_3:b , ME_OR2_B:iu_hold_gate_4:b |
Connects up to: | fp_fpc:fpqst:hld_dirreg |
Connects down to: | Mpc_cntl:pc_cntl:hld_lgens |
Connects up to: | Miuchip:decode:hld_lgens |
Connects down to: | Mpc:pc:hld_lgens , Mdecode:decode:hld_lgens |
Connects up to: | Miuchip:pc:hld_lgens |
Connects up to: | Mdecode:pc_cntl:hld_lgens |
Connects down to: | Mflipflop_30:last_gen_reg_30:enable_l , Mflipflop_30:ll_gen_reg_30:enable_l |
Connects down to: | Mflipflop_1:llastc_reg_1:enable_l |
Connects down to: | Mflipflop_1:hld_llc_reg_1:out |
Connects down to: | MflipflopR_31:mfar_reg_31:enable_l |
Connects up to: | mmu:MMU_dp:hld_mfar |
Connects down to: | m_mmu_cntl:MMU_cntl:hld_mfar , dp_mmu:MMU_dp:hld_mfar |
Connects down to: | rl_mmu_regs:mmu_regs:hld_mfar |
Connects up to: | mmu:MMU_cntl:hld_mfar |
Connects up to: | m_mmu_cntl:mmu_regs:hld_mfar |
Connects down to: | MflipflopR_6:mid_6:enable_l |
Connects down to: | MflipflopR_1:mid_1:enable_l |
Connects down to: | GReg1:ffh_pa25:hld , GReg1:ffh_pa26:hld , GReg1:ffh_pa27:hld , GReg1:ffh_dpct0:hld , GReg1:ffh_dpct1:hld |
Connects down to: | rl_mmu_regs:mmu_regs:hld_mmu_cr , rl_va_mux:va_muxl:hld_mmu_cr |
Connects down to: | MflipflopR_15:mmu_cr_rega_15:enable_l , MflipflopR_4:mmu_cr_regw_4:enable_l |
Connects up to: | m_mmu_cntl:mmu_regs:hld_mmu_cr |
Connects up to: | m_mmu_cntl:va_muxl:hld_mmu_cr |
Connects down to: | GReg1:ffh_pa02:hld |
Connects down to: | GReg2:ffh_col_mm_hi_in:hld , Mux2_2:mx_col_mm_hi:sel1 |
Connects up to: | rl_mcb:cr_addr:mx_hld_mm_pa |
Connects up to: | rl_mcb:mcb_lgc:mx_hld_mm_pa |
Connects down to: | Mspecial_reg_control:special_reg_control:hld_pilefec |
Connects up to: | Miuchip:decode:hld_pilefec |
Connects down to: | Mpsr:psr_mod:hld_pilefec |
Connects up to: | Miuchip:exec:hld_pilefec |
Connects down to: | Mdecode:decode:hld_pilefec , Mexec:exec:hld_pilefec |
Connects up to: | Mdecode:special_reg_control:hld_pilefec |
Connects down to: | MflipflopR_32:sfar_32:enable_l |
Connects up to: | mmu:MMU_dp:hld_sfar |
Connects down to: | m_mmu_cntl:MMU_cntl:hold_sfar , dp_mmu:MMU_dp:hld_sfar |
Connects down to: | rl_mmu_regs:mmu_regs:hld_sfar , rl_va_mux:va_muxl:hld_sfar |
Connects up to: | m_mmu_cntl:mmu_regs:hld_sfar |
Connects up to: | m_mmu_cntl:va_muxl:hld_sfar |
Connects down to: | rl_mmu_regs:mmu_regs:hld_sfsr , rl_va_mux:va_muxl:hld_sfsr |
Connects up to: | m_mmu_cntl:mmu_regs:hld_sfsr |
Connects up to: | m_mmu_cntl:va_muxl:hld_sfsr |
Connects down to: | MflipflopR_3:sscr0_3:enable_l |
Connects down to: | MflipflopR_3:sscr1_3:enable_l |
Connects down to: | MflipflopR_3:sscr2_3:enable_l |
Connects down to: | MflipflopR_3:sscr3_3:enable_l |
Connects down to: | MflipflopR_3:sscr4_3:enable_l |
Connects down to: | Mspecial_reg_control:special_reg_control:hld_tba |
Connects up to: | Miuchip:decode:hld_tba |
Connects down to: | Mtbr:tbr_mod:hld_tba |
Connects up to: | Miuchip:exec:hld_tba |
Connects down to: | Mdecode:decode:hld_tba , Mexec:exec:hld_tba |
Connects up to: | Mdecode:special_reg_control:hld_tba |
Connects down to: | Mflipflop_20:tba_master_20:enable_l |
Connects up to: | Mexec:tbr_mod:hld_tba |
Connects down to: | rl_mmu_regs:mmu_regs:hld_trcr , rl_va_mux:va_muxl:hld_trcr |
Connects up to: | m_mmu_cntl:va_muxl:hld_trcr |
Connects down to: | MflipflopR_6:trcr_addr_ff_6:enable_l |
Connects down to: | Mspecial_reg_control:special_reg_control:hld_tt |
Connects up to: | Miuchip:decode:hld_tt |
Connects down to: | Mtbr:tbr_mod:hld_tt |
Connects up to: | Miuchip:exec:hld_tt |
Connects down to: | Mdecode:decode:hld_tt , Mexec:exec:hld_tt |
Connects up to: | Mdecode:special_reg_control:hld_tt |
Connects down to: | Mflipflop_8:tt_master_8:enable_l |
Connects up to: | Mexec:tbr_mod:hld_tt |
Connects down to: | Mflipflop_12:w_iexc_reg_12:enable_l |
Connects down to: | Mspecial_reg_control:special_reg_control:hld_wim |
Connects up to: | Miuchip:decode:hld_wim |
Connects down to: | Mwim:wim_mod:hld_wim |
Connects up to: | Miuchip:exec:hld_wim |
Connects down to: | Mdecode:decode:hld_wim , Mexec:exec:hld_wim |
Connects up to: | Mdecode:special_reg_control:hld_wim |
Connects down to: | Mflipflop_8:wim_master_8:enable_l |
Connects up to: | Mexec:wim_mod:hld_wim |
Connects up to: | Mdecode:alu_control:hld_y |
Connects down to: | Malu_control:alu_control:hld_y |
Connects up to: | Miuchip:decode:hld_y |
Connects down to: | My:y_mod:hld_y |
Connects up to: | Miuchip:exec:hld_y |
Connects down to: | Mdecode:decode:hld_y , Mexec:exec:hld_y |
Connects down to: | Mflipflop_32:ymaster_32:enable_l |
Connects up to: | Mexec:y_mod:hld_y |