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Signals index

H
 H : ADFFRHA : input
Connects up to:Mflipflop_rh:dff:enable_l 
 H : AO12A : input
 H : AO12C : input
 H : AOI2222A : input
 H : ASFFHA : input
Connects up to:Mflipflop_sh:dff:enable_l , Mflipflop:dff:enable_l 
 H : ASFFRHA : input
Connects up to:Mflipflop_srh:dff:enable_l , MflipflopR:dff:enable_l , rsflop:dff:global_reset , rsflop:dff:reset , rsflop:dff:hold 
 h : ME_AND8 : input
Connects down to:JAND8B:i:A8 
Connects up to:Exception:zxd:BM 
 H : ME_FREG_H_32 : input
Connects down to:Mflipflop:f00:enable_l , Mflipflop:f01:enable_l , Mflipflop:f02:enable_l , Mflipflop:f03:enable_l , Mflipflop:f04:enable_l , Mflipflop:f05:enable_l , Mflipflop:f06:enable_l , Mflipflop:f07:enable_l , Mflipflop:f08:enable_l , Mflipflop:f09:enable_l , Mflipflop:f10:enable_l , Mflipflop:f11:enable_l , Mflipflop:f12:enable_l , Mflipflop:f13:enable_l , Mflipflop:f14:enable_l , Mflipflop:f15:enable_l , Mflipflop:f16:enable_l , Mflipflop:f17:enable_l , Mflipflop:f18:enable_l , Mflipflop:f19:enable_l , Mflipflop:f20:enable_l , Mflipflop:f21:enable_l , Mflipflop:f22:enable_l , Mflipflop:f23:enable_l , Mflipflop:f24:enable_l , Mflipflop:f25:enable_l , Mflipflop:f26:enable_l , Mflipflop:f27:enable_l , Mflipflop:f28:enable_l , Mflipflop:f29:enable_l , Mflipflop:f30:enable_l , Mflipflop:f31:enable_l 
Connects up to:fp_qst:ir_reg_d:hold_d 
 h : ME_NAND8 : input
Connects down to:JNAND8C:i:A8 
 h : ME_NAND8_B : input
Connects down to:JNAND8C:i:A8 
Connects up to:CheckOverflow:g10:FracResult 
 h : ME_O2222AI : input
Connects down to:AG2222A:i:D2 
 h : ME_O2222AI_B : input
Connects down to:AG2222A:i:D2 
 h : ME_OR11 : input
Connects down to:JNOR8C:u0:A8 
Connects up to:Exception:g10:BM 
 h : ME_OR12 : input
Connects down to:JNOR8C:u0:A8 
 h : ME_OR8 : input
Connects down to:JOR8B:i:A8 
Connects up to:ShiftRightCtl:g80:Stky8 
 H : MSFFHA : input
 H : MSFFRHA : input
 H1 : JD2X8A : input
 h1 : Mccdisp : integer
 H1 : MJD2X8A : input
 H2 : JD2X8A : input
 h2 : Mccdisp : integer
 H2 : MJD2X8A : input
 hack_par : dp_mmu : wire
 half_bytemark : Mdcache_control : wire
 half_store_d : Mdecode : output
Connects down to:Mir_control:ir_control:half_store_d 
Connects up to:Miuchip:decode:half_store_d 
 half_store_d : Mir_control : output wire
Connects up to:Mdecode:ir_control:half_store_d 
 half_store_d : Miuchip : wire
Connects down to:Mdecode:decode:half_store_d , Mregfile:regfile:half_store_d 
 half_store_d : Mregfile : input
Connects up to:Miuchip:regfile:half_store_d 
 half_store_d_in : Mregfile : wire
Connects down to:Mflipflop_1:half_st_e_reg_1:din 
 half_store_d_scan : Mregfile : wire
 half_store_e : Mregfile : wire
Connects down to:Mflipflop_1:half_st_e_reg_1:out 
 head : sastasks : integer
 help_count_out : Mpipec_help_ilock : wire
 help_ctr : Malu_control : input
Connects down to:Mflipflop_1:phelp_ctr5_reg_1:din 
Connects up to:Mdecode:alu_control:help_ctr 
 help_ctr : Mdata_byp1_2 : input
Connects up to:Mdecode:data_byp1_2:help_ctr 
 help_ctr : Mdata_byp2 : input
Connects up to:Mdecode:data_byp2:help_ctr 
 help_ctr : Mdecode : wire
Connects down to:Mpipec_help_ilock:pipec_help_ilock:help_ctr , Mdata_byp1_2:data_byp1_2:help_ctr , Mdata_byp2:data_byp2:help_ctr , Malu_control:alu_control:help_ctr , Mspecial_reg_control:special_reg_control:help_ctr_0 , Mspecial_reg_control:special_reg_control:help_ctr_1 
 help_ctr : Mpipec_help_ilock : output wire
Connects down to:Mflipflop_6:help_ctr_reg_6:out 
Connects up to:Mdecode:pipec_help_ilock:help_ctr 
 help_ctr_0 : Mspecial_reg_control : input
Connects up to:Mdecode:special_reg_control:help_ctr 
 help_ctr_1 : Mspecial_reg_control : input
Connects up to:Mdecode:special_reg_control:help_ctr 
 hexaddress : pcimaster_fm : reg
 HI : stat_ctl : wire
Connects down to:ME_TIEOFF:toff:VDD , ME_INVA:g0:a , ME_INVA:g1:a , ME_INVA:g2:a , ME_INVA:g3:a , ME_INVA:g4:a , ME_INVA:g6:a , ME_INVA:g7:a , ME_INVA:g8:a 
 hidiv_in_d : Malu_control : input
Connects up to:Mdecode:alu_control:hidiv_in_d 
 hidiv_in_d : Mdecode : wire
Connects down to:Mpipec_im_id:pipec_im_id:hidiv_in_d , Malu_control:alu_control:hidiv_in_d 
 hidiv_in_d : Mpipec_im_id : output wire
Connects up to:Mdecode:pipec_im_id:hidiv_in_d 
 highest_req : pcimonitor_fm : integer
 HIGHFRQ : PLL300CBFI : input
 high_2 : alu34 : wire
 high_2 : Mexec : wire
Connects down to:Mflipflop_2:result_high2_reg_2:din 
 high_2_1 : Malu_control : input
Connects up to:Mdecode:alu_control:high_2_1 
 high_2_1 : Mdecode : input
Connects down to:Malu_control:alu_control:high_2_1 
Connects up to:Miuchip:decode:high_2_1 
 high_2_1 : Mexec : output wire
Connects up to:Miuchip:exec:high_2_1 
 high_2_1 : Miuchip : wire
Connects down to:Mdecode:decode:high_2_1 , Mexec:exec:high_2_1 
 high_2_almost : alu34 : wire
 high_in : Mrf_xlate : wire
 himul_in_d : Malu_control : input
Connects up to:Mdecode:alu_control:himul_in_d 
 himul_in_d : Mdecode : wire
Connects down to:Mpipec_im_id:pipec_im_id:himul_in_d , Malu_control:alu_control:himul_in_d 
 himul_in_d : Mpipec_im_id : output wire
Connects up to:Mdecode:pipec_im_id:himul_in_d 
 hit : cam : wire
Connects down to:CAM_LINE:tag00:hit , CAM_LINE:tag01:hit , CAM_LINE:tag02:hit , CAM_LINE:tag03:hit , CAM_LINE:tag04:hit , CAM_LINE:tag05:hit , CAM_LINE:tag06:hit , CAM_LINE:tag07:hit , CAM_LINE:tag08:hit , CAM_LINE:tag09:hit , CAM_LINE:tag10:hit , CAM_LINE:tag11:hit , CAM_LINE:tag12:hit , CAM_LINE:tag13:hit , CAM_LINE:tag14:hit , CAM_LINE:tag15:hit , CAM_LINE:tag16:hit , CAM_LINE:tag17:hit , CAM_LINE:tag18:hit , CAM_LINE:tag19:hit , CAM_LINE:tag20:hit , CAM_LINE:tag21:hit , CAM_LINE:tag22:hit , CAM_LINE:tag23:hit , CAM_LINE:tag24:hit , CAM_LINE:tag25:hit , CAM_LINE:tag26:hit , CAM_LINE:tag27:hit , CAM_LINE:tag28:hit , CAM_LINE:tag29:hit , CAM_LINE:tag30:hit , CAM_LINE:tag31:hit 
 hit : CAM_LINE : output
Connects up to:cam:tag00:hit , cam:tag01:hit , cam:tag02:hit , cam:tag03:hit , cam:tag04:hit , cam:tag05:hit , cam:tag06:hit , cam:tag07:hit , cam:tag08:hit , cam:tag09:hit , cam:tag10:hit , cam:tag11:hit , cam:tag12:hit , cam:tag13:hit , cam:tag14:hit , cam:tag15:hit , cam:tag16:hit , cam:tag17:hit , cam:tag18:hit , cam:tag19:hit , cam:tag20:hit , cam:tag21:hit , cam:tag22:hit , cam:tag23:hit , cam:tag24:hit , cam:tag25:hit , cam:tag26:hit , cam:tag27:hit , cam:tag28:hit , cam:tag29:hit , cam:tag30:hit , cam:tag31:hit 
 hit : iocam : wire
Connects down to:IOCAM_LINE:tag00:hit , IOCAM_LINE:tag01:hit , IOCAM_LINE:tag02:hit , IOCAM_LINE:tag03:hit , IOCAM_LINE:tag04:hit , IOCAM_LINE:tag05:hit , IOCAM_LINE:tag06:hit , IOCAM_LINE:tag07:hit , IOCAM_LINE:tag08:hit , IOCAM_LINE:tag09:hit , IOCAM_LINE:tag10:hit , IOCAM_LINE:tag11:hit , IOCAM_LINE:tag12:hit , IOCAM_LINE:tag13:hit , IOCAM_LINE:tag14:hit , IOCAM_LINE:tag15:hit 
 hit : IOCAM_LINE : output
Connects up to:iocam:tag00:hit , iocam:tag01:hit , iocam:tag02:hit , iocam:tag03:hit , iocam:tag04:hit , iocam:tag05:hit , iocam:tag06:hit , iocam:tag07:hit , iocam:tag08:hit , iocam:tag09:hit , iocam:tag10:hit , iocam:tag11:hit , iocam:tag12:hit , iocam:tag13:hit , iocam:tag14:hit , iocam:tag15:hit 
 hit : pcislave_fm : reg
 hit_cntxt : CAM_LINE : wire
 hit_cntxt : IOCAM_LINE : wire
 hit_cntxt2 : CAM_LINE : wire
 hit_cntxt2 : IOCAM_LINE : wire
 hit_delayer_cycles : pcislave_fm : integer
 hit_iopte : CAM_LINE : wire
 hit_iopte : IOCAM_LINE : wire
 hit_last : pcislave_fm : reg
 hit_lvl0 : CAM_LINE : wire
 hit_lvl0 : IOCAM_LINE : wire
 hit_lvl02 : CAM_LINE : wire
 hit_lvl02 : IOCAM_LINE : wire
 hit_lvl1 : CAM_LINE : wire
 hit_lvl1 : IOCAM_LINE : wire
 hit_lvl12 : CAM_LINE : wire
 hit_lvl12 : IOCAM_LINE : wire
 hit_lvl2 : CAM_LINE : wire
 hit_lvl2 : IOCAM_LINE : wire
 hit_lvl22 : CAM_LINE : wire
 hit_lvl22 : IOCAM_LINE : wire
 hit_no : cam : integer
 hit_no : iocam : integer
 hit_nx : pcislave_fm : reg
 hit_ptp : CAM_LINE : wire
 hit_ptp : IOCAM_LINE : wire
 hit_resolved : pcislave_fm : reg
 hi_addr_hold : addr_reg : reg
 hi_addr_hold_d1 : addr_reg : reg
 HLD : AMUXFFA : input
 hld : GReg1 : input
Connects down to:Mflipflop_1:GReg_1_1:enable_l 
Connects up to:HDReg:InReg:Gnd , HDReg:OReg_half:Gnd , rl_col_row_addr:ffh_gaddr_28:gaddr_hld , rl_col_row_addr:ffh_gaddr_21:gaddr_hld , rl_col_row_addr:ffh_gaddr_12:gaddr_hld , rl_dpc_cont:ffh_dpct2:ct2_reg_hld , rl_dpc_core:Pari0:in_hld , rl_dpc_core:Pari1:in_hld , rl_mcb_lgc:ffh_pa25:hld_mm , rl_mcb_lgc:ffh_pa26:hld_mm , rl_mcb_lgc:ffh_pa27:hld_mm , rl_mcb_lgc:ffh_dpct0:hld_mm , rl_mcb_lgc:ffh_dpct1:hld_mm , rl_mcb_lgc:ffh_wrp06n:Gnd , rl_mcb_lgc:ffh_dead_idle_reg:dead_idle_hld , rl_mcb_lgc:ffh_pa02:hld_mm_cas 
 hld : GReg10 : input
Connects down to:Mflipflop_10:GReg_10_10:enable_l 
 hld : GReg11 : input
Connects down to:Mflipflop_11:GReg_11_11:enable_l 
 hld : GReg12 : input
Connects down to:Mflipflop_12:GReg_12_12:enable_l 
Connects up to:rl_col_row_addr:ffh_row_mm_reg:gaddr_hld 
 hld : GReg2 : input
Connects down to:Mflipflop_2:GReg_2_2:enable_l 
Connects up to:rl_col_row_addr:ffh_mm_mem_dbg_n:mm_issue_req , rl_col_row_addr:ffh_col_mm_hi_in:hld_mm_pa 
 hld : GReg3 : input
Connects down to:Mflipflop_3:GReg_3_3:enable_l 
Connects up to:rl_col_row_addr:ffh_gaddr_27_25:gaddr_hld , rl_mcb_sm:ffh_srcreg54:cyc_hld , rl_mcb_sm:ffh_srcreg54_2:cyc_hld 
 hld : GReg32 : input
Connects down to:Mflipflop_32:GReg_32_32:enable_l 
Connects up to:rl_dpc_dpath:in0:in_hld , rl_dpc_dpath:in1:in_hld , rl_dpc_dpath:grout0:gr_hld , rl_dpc_dpath:grout1:gr_hld , rl_dpc_dpath:grout2:gr_hld , rl_dpc_dpath:grout3:gr_hld , rl_dpc_dpath:out0:out_hld_0 , rl_dpc_dpath:out1:out_hld_1 , rl_memif_minor:out2:out_hld_2 , rl_memif_minor:out3:out_hld_3 
 hld : GReg4 : input
Connects down to:Mflipflop_4:GReg_4_4:enable_l 
Connects up to:rl_col_row_addr:ffh_bm:odat_hld , rl_mcb_sm:ffh_srcreg30:cyc_hld_read , rl_mcb_sm:ffh_srcreg30_2:cyc_hld_read 
 hld : GReg5 : input
Connects down to:Mflipflop_5:GReg_5_5:enable_l 
 hld : GReg6 : input
Connects down to:Mflipflop_6:GReg_6_6:enable_l 
 hld : GReg7 : input
Connects down to:Mflipflop_7:GReg_7_7:enable_l 
Connects up to:rl_reqtimer:ffh_reqtim:hld 
 hld : GReg8 : input
Connects down to:Mflipflop_8:GReg_8_8:enable_l 
 hld : GReg9 : input
Connects down to:Mflipflop_9:GReg_9_9:enable_l 
Connects up to:rl_col_row_addr:ffh_gaddr_11_3:gaddr_hld 
 hld : GRegr : input
Connects down to:MflipflopR_1:Greg_r_1:enable_l 
Connects up to:rl_mcb_lgc:freql:sync_t2 , rl_mcb_lgc:frrdl:sync_t2 , rl_mcb_lgc:ffh_mbsydly_1:Gnd , rl_mcb_lgc:ffh_mbsydly_2:Gnd , rl_mcb_lgc:ffh_mbsydly_3:Gnd , rl_mcb_lgc:ffh_mbsydly_4:Gnd , rl_mcb_lgc:ffh_mbsydly_5:Gnd , rl_mcb_lgc:ffh_mbsydly_6:Gnd 
 hld : rl_reqtimer : wire
Connects down to:GReg7:ffh_reqtim:hld 
 hld_afar : dp_mmu : input
Connects down to:MflipflopR_31:afar_31:enable_l 
Connects up to:mmu:MMU_dp:hld_afar 
 hld_afar : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_afar , dp_mmu:MMU_dp:hld_afar 
 hld_afar : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:hld_afar 
Connects up to:mmu:MMU_cntl:hld_afar 
 hld_afar : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:hld_afar 
 hld_afx_qlvl : rl_mmu_regs : wire
Connects down to:MflipflopR_1:afx_qlvl_ff_1:enable_l 
 hld_backup : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:beis_reg:enable_l , Mflipflop_h_32:bois_reg:enable_l 
 hld_backup : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hld_backup 
Connects up to:Miuchip:decode:hld_backup 
 hld_backup : Miuchip : wire
Connects down to:Mqueue:queue:hld_backup , Mdecode:decode:hld_backup 
 hld_backup : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hld_backup 
 hld_backup : Mqueue : input
Connects up to:Miuchip:queue:hld_backup 
 hld_backup_almost : Mpc_cntl : wire
Connects down to:Mflipflop_1:hld_backup_almost_reg_1:out 
 hld_backup_real : Mqueue : wire
Connects down to:Mflipflop_32:ic_even_bu_reg_32:enable_l , Mflipflop_32:ic_odd_bu_reg_32:enable_l , Mflipflop_11:ic_iexc_bu_11:enable_l 
 hld_car_mar : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hld_car_mar 
Connects up to:Miuchip:decode:hld_car_mar 
 hld_car_mar : Miuchip : wire
Connects down to:Mpc:pc:hld_car_mar , Mdecode:decode:hld_car_mar 
 hld_car_mar : Mpc : input
Connects up to:Miuchip:pc:hld_car_mar 
 hld_car_mar : Mpc_cntl : output wire
Connects down to:Mflipflop_1:hld_llc_reg_1:din 
Connects up to:Mdecode:pc_cntl:hld_car_mar 
 hld_car_mar_real : Mpc : wire
Connects down to:Mflipflop_30:car_register_30:enable_l 
 hld_ctpr : dp_mmu : input
Connects down to:MflipflopR_18:ctpr_18:enable_l 
Connects up to:mmu:MMU_dp:hld_ctpr 
 hld_ctpr : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_ctpr , dp_mmu:MMU_dp:hld_ctpr 
 hld_ctpr : m_mmu_cntl : output
Connects down to:rl_va_mux:va_muxl:hld_ctpr 
Connects up to:mmu:MMU_cntl:hld_ctpr 
 hld_ctpr : rl_va_mux : output wire
Connects up to:m_mmu_cntl:va_muxl:hld_ctpr 
 hld_cxr : dp_mmu : input
Connects down to:MflipflopR_8:tlb_cxr_8:enable_l 
Connects up to:mmu:MMU_dp:hld_cxr 
 hld_cxr : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_cxr , dp_mmu:MMU_dp:hld_cxr 
 hld_cxr : m_mmu_cntl : output
Connects down to:rl_va_mux:va_muxl:hld_cxr 
Connects up to:mmu:MMU_cntl:hld_cxr 
 hld_cxr : rl_va_mux : output wire
Connects up to:m_mmu_cntl:va_muxl:hld_cxr 
 hld_dir2 : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hld_dir2 
Connects up to:Miuchip:decode:hld_dir2 
 hld_dir2 : Miuchip : wire
Connects down to:Mqueue:queue:hld_dir2 , Mdecode:decode:hld_dir2 
 hld_dir2 : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hld_dir2 
 hld_dir2 : Mqueue : input
Connects up to:Miuchip:queue:hld_dir2 
 hld_dir2_real : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:oops_reg:enable_l , Mflipflop_h_32:oops_f_reg:enable_l 
 hld_dir2_real : Mpc_cntl : wire
Connects down to:Mflipflop_10:backup_dir_reg_10:enable_l , Mflipflop_9:backup_biexc_reg_9:enable_l 
 hld_dir2_real : Mqueue : wire
Connects down to:Mflipflop_30:p_fold_aa_reg_30:enable_l , Mflipflop_32:backup_dir_reg_32:enable_l , Mflipflop_11:backup_iexc_reg_11:enable_l 
 hld_dirreg : fpufpc : input
Connects down to:fp_fpc:fpfpc:hld_dirreg 
Connects up to:ssparc_core:ssparc_fpu:hld_dirreg 
 hld_dirreg : fp_fpc : input
Connects down to:fp_qst:fpqst:hld_ir_d 
Connects up to:fpufpc:fpfpc:hld_dirreg 
 hld_dirreg : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:oops_reg:din , Mflipflop_h_32:oops_f_reg:din 
 hld_dirreg : Mdecode : output
Connects down to:Mir_control:ir_control:hld_dirreg , Minterface:interface:hld_dirreg , Mir:ir:hld_dirreg 
Connects up to:Miuchip:decode:hld_dirreg 
 hld_dirreg : Minterface : input
Connects up to:Mdecode:interface:hld_dirreg 
 hld_dirreg : Mir : input
Connects up to:Mdecode:ir:hld_dirreg 
 hld_dirreg : Mir_control : output wire
Connects up to:Mdecode:ir_control:hld_dirreg 
 hld_dirreg : Miu : output
Connects down to:Miuchip:iuchip:hld_dirreg 
Connects up to:ssparc_core:iu:hld_dirreg 
 hld_dirreg : Miuchip : output
Connects down to:Mqueue:queue:hld_dirreg , Mdecode:decode:hld_dirreg 
Connects up to:Miu:iuchip:hld_dirreg 
 hld_dirreg : Mqueue : input
Connects up to:Miuchip:queue:hld_dirreg 
 hld_dirreg : Mregfile : input
Connects down to:Mflipflop_5:brs1_decm_reg_5:enable_l , Mflipflop_5:brs2_decm_reg_5:enable_l 
Connects up to:Miuchip:regfile:hld_dirreg_rf 
 hld_dirreg : ssparc_core : wire
Connects down to:Miu:iu:hld_dirreg , fpufpc:ssparc_fpu:hld_dirreg 
 hld_dirreg_real : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:dis_reg:enable_l 
 hld_dirreg_real : Minterface : wire
Connects down to:Mflipflop_1:mm_iacc_exc_d_reg_1:enable_l , Mflipflop_1:mm_iacc_mm_reg_1:enable_l , Mflipflop_1:mm_iac_err_tlb_1:enable_l , Mflipflop_1:mm_iacc_wp_exc_d_reg_1:enable_l , Mflipflop_1:parity_error_d_reg_1:enable_l 
 hld_dirreg_real : Mir : wire
Connects down to:Mflipflop_5:d_rs1_reg_5:enable_l , Mflipflop_32:dir_reg_32:enable_l , Mflipflop_1:ifori_dummy31_reg_1:enable_l , Mflipflop_1:ifori_dummy24_reg_1:enable_l , Mflipflop_1:ifori_dummy21_reg_1:enable_l , Mflipflop_1:ifori_dummy20_reg_1:enable_l , Mflipflop_1:ifori_dummy19_reg_1:enable_l , Mflipflop_12:d_iexc_reg_12:enable_l 
 hld_dirreg_real : Mqueue : wire
Connects down to:Mflipflop_32:dummy_dir_reg_32:enable_l 
 hld_dirreg_rf : Mdecode : output
Connects down to:Mir_control:ir_control:hld_dirreg_rf 
Connects up to:Miuchip:decode:hld_dirreg_rf 
 hld_dirreg_rf : Mir_control : output wire
Connects up to:Mdecode:ir_control:hld_dirreg_rf 
 hld_dirreg_rf : Miuchip : wire
Connects down to:Mdecode:decode:hld_dirreg_rf , Mregfile:regfile:hld_dirreg 
 hld_dpar : dp_mmu : input
Connects down to:MflipflopR_31:dpar_reg_31:enable_l 
Connects up to:mmu:MMU_dp:hld_dpar 
 hld_dpar : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_dpar , dp_mmu:MMU_dp:hld_dpar 
 hld_dpar : m_mmu_cntl : output
Connects down to:rl_par_cntl:par_cntl:dpar_valid , rl_mmu_regs:mmu_regs:dpar_valid 
Connects up to:mmu:MMU_cntl:hld_dpar 
 hld_dpc : Mdecode : output
Connects down to:Mpc_control:pc_control:hld_dpc 
Connects up to:Miuchip:decode:hld_dpc 
 hld_dpc : Miuchip : wire
Connects down to:Mpc:pc:hld_dpc , Mdecode:decode:hld_dpc 
 hld_dpc : Mpc : input
Connects up to:Miuchip:pc:hld_dpc 
 hld_dpc : Mpc_control : output
Connects up to:Mdecode:pc_control:hld_dpc 
 hld_dsb2 : Malu_control : wire
Connects down to:Mflipflop_1:dsign_bit2_reg_1:enable_l 
 hld_dum_dpc : Mdecode : output
Connects down to:Mpc_control:pc_control:hld_dum_dpc 
Connects up to:Miuchip:decode:hld_dum_dpc 
 hld_dum_dpc : Miuchip : wire
Connects down to:Mqueue:queue:hld_dum_dpc , Mdecode:decode:hld_dum_dpc 
 hld_dum_dpc : Mpc_control : output wire
Connects up to:Mdecode:pc_control:hld_dum_dpc 
 hld_dum_dpc : Mqueue : input
Connects up to:Miuchip:queue:hld_dum_dpc 
 hld_dum_dpc_real : Mqueue : wire
Connects down to:Mflipflop_30:dummy_dpc_reg_30:enable_l 
 hld_filladdr : Mpc : wire
Connects down to:Mflipflop_9:fill_adr_hi_reg_9:enable_l 
 hld_ibar : dp_mmu : input
Connects down to:MflipflopR_17:ibar_17:enable_l 
Connects up to:mmu:MMU_dp:hld_ibar 
 hld_ibar : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_ibar , dp_mmu:MMU_dp:hld_ibar 
 hld_ibar : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:hld_ibar 
Connects up to:mmu:MMU_cntl:hld_ibar 
 hld_ibar : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:hld_ibar 
 hld_io_cr : rl_mmu_regs : wire
Connects down to:MflipflopR_4:io_cr_4:enable_l 
 hld_ipar : dp_mmu : input
Connects down to:MflipflopR_31:ipar_reg_31:enable_l 
Connects up to:mmu:MMU_dp:hld_ipar 
 hld_ipar : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_ipar , dp_mmu:MMU_dp:hld_ipar 
 hld_ipar : m_mmu_cntl : output
Connects down to:rl_par_cntl:par_cntl:ipar_valid , rl_mmu_regs:mmu_regs:ipar_valid 
Connects up to:mmu:MMU_cntl:hld_ipar 
 hld_ir_d : fp_qst : input
Connects down to:ME_OR2_B:iu_hold_gate_1:b , ME_OR2_B:iu_hold_gate_2:b , ME_OR2_B:iu_hold_gate_3:b , ME_OR2_B:iu_hold_gate_4:b 
Connects up to:fp_fpc:fpqst:hld_dirreg 
 hld_lgens : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hld_lgens 
Connects up to:Miuchip:decode:hld_lgens 
 hld_lgens : Miuchip : wire
Connects down to:Mpc:pc:hld_lgens , Mdecode:decode:hld_lgens 
 hld_lgens : Mpc : input
Connects up to:Miuchip:pc:hld_lgens 
 hld_lgens : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hld_lgens 
 hld_lgens_real : Mpc : wire
Connects down to:Mflipflop_30:last_gen_reg_30:enable_l , Mflipflop_30:ll_gen_reg_30:enable_l 
 hld_llc : Mpc_cntl : wire
Connects down to:Mflipflop_1:llastc_reg_1:enable_l 
 hld_llc_almost : Mpc_cntl : wire
Connects down to:Mflipflop_1:hld_llc_reg_1:out 
 hld_mfar : dp_mmu : input
Connects down to:MflipflopR_31:mfar_reg_31:enable_l 
Connects up to:mmu:MMU_dp:hld_mfar 
 hld_mfar : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hld_mfar , dp_mmu:MMU_dp:hld_mfar 
 hld_mfar : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:hld_mfar 
Connects up to:mmu:MMU_cntl:hld_mfar 
 hld_mfar : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:hld_mfar 
 hld_mid : rl_mmu_regs : wire
Connects down to:MflipflopR_6:mid_6:enable_l 
 hld_mid_standby : rl_mmu_regs : wire
Connects down to:MflipflopR_1:mid_1:enable_l 
 hld_mm : rl_mcb_lgc : wire
Connects down to:GReg1:ffh_pa25:hld , GReg1:ffh_pa26:hld , GReg1:ffh_pa27:hld , GReg1:ffh_dpct0:hld , GReg1:ffh_dpct1:hld 
 hld_mmu_cr : m_mmu_cntl : wire
Connects down to:rl_mmu_regs:mmu_regs:hld_mmu_cr , rl_va_mux:va_muxl:hld_mmu_cr 
 hld_mmu_cr : rl_mmu_regs : input
Connects down to:MflipflopR_15:mmu_cr_rega_15:enable_l , MflipflopR_4:mmu_cr_regw_4:enable_l 
Connects up to:m_mmu_cntl:mmu_regs:hld_mmu_cr 
 hld_mmu_cr : rl_va_mux : output wire
Connects up to:m_mmu_cntl:va_muxl:hld_mmu_cr 
 hld_mm_cas : rl_mcb_lgc : wire
Connects down to:GReg1:ffh_pa02:hld 
 hld_mm_pa : rl_col_row_addr : input
Connects down to:GReg2:ffh_col_mm_hi_in:hld , Mux2_2:mx_col_mm_hi:sel1 
Connects up to:rl_mcb:cr_addr:mx_hld_mm_pa 
 hld_mm_pa : rl_mcb_lgc : output
Connects up to:rl_mcb:mcb_lgc:mx_hld_mm_pa 
 hld_mreq_reg : rl_mmu_lgc : wire
 hld_pilefec : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hld_pilefec 
Connects up to:Miuchip:decode:hld_pilefec 
 hld_pilefec : Mexec : input
Connects down to:Mpsr:psr_mod:hld_pilefec 
Connects up to:Miuchip:exec:hld_pilefec 
 hld_pilefec : Miuchip : wire
Connects down to:Mdecode:decode:hld_pilefec , Mexec:exec:hld_pilefec 
 hld_pilefec : Mpsr : input
Connects down to:Mcwp:cwp_mod:w_wrpsr_l , Mflipflop_4:pil_master_4:enable_l , Mflipflop_1:ef_master_1:enable_l , Mflipflop_1:ec_master_1:enable_l , Mflipflop_1:de_master_1:enable_l , Mflipflop_1:de_sup_master_1:enable_l 
Connects up to:Mexec:psr_mod:hld_pilefec 
 hld_pilefec : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hld_pilefec 
 hld_sfar : dp_mmu : input
Connects down to:MflipflopR_32:sfar_32:enable_l 
Connects up to:mmu:MMU_dp:hld_sfar 
 hld_sfar : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hold_sfar , dp_mmu:MMU_dp:hld_sfar 
 hld_sfar : m_mmu_cntl : wire
Connects down to:rl_mmu_regs:mmu_regs:hld_sfar , rl_va_mux:va_muxl:hld_sfar 
 hld_sfar : rl_mmu_regs : input
Connects up to:m_mmu_cntl:mmu_regs:hld_sfar 
 hld_sfar : rl_va_mux : output wire
Connects up to:m_mmu_cntl:va_muxl:hld_sfar 
 hld_sfsr : m_mmu_cntl : wire
Connects down to:rl_mmu_regs:mmu_regs:hld_sfsr , rl_va_mux:va_muxl:hld_sfsr 
 hld_sfsr : rl_mmu_regs : input
Connects up to:m_mmu_cntl:mmu_regs:hld_sfsr 
 hld_sfsr : rl_va_mux : output wire
Connects up to:m_mmu_cntl:va_muxl:hld_sfsr 
 hld_sscr0 : rl_mmu_regs : wire
Connects down to:MflipflopR_3:sscr0_3:enable_l 
 hld_sscr1 : rl_mmu_regs : wire
Connects down to:MflipflopR_3:sscr1_3:enable_l 
 hld_sscr2 : rl_mmu_regs : wire
Connects down to:MflipflopR_3:sscr2_3:enable_l 
 hld_sscr3 : rl_mmu_regs : wire
Connects down to:MflipflopR_3:sscr3_3:enable_l 
 hld_sscr4 : rl_mmu_regs : wire
Connects down to:MflipflopR_3:sscr4_3:enable_l 
 hld_tba : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hld_tba 
Connects up to:Miuchip:decode:hld_tba 
 hld_tba : Mexec : input
Connects down to:Mtbr:tbr_mod:hld_tba 
Connects up to:Miuchip:exec:hld_tba 
 hld_tba : Miuchip : wire
Connects down to:Mdecode:decode:hld_tba , Mexec:exec:hld_tba 
 hld_tba : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hld_tba 
 hld_tba : Mtbr : input
Connects down to:Mflipflop_20:tba_master_20:enable_l 
Connects up to:Mexec:tbr_mod:hld_tba 
 hld_trcr : m_mmu_cntl : wire
Connects down to:rl_mmu_regs:mmu_regs:hld_trcr , rl_va_mux:va_muxl:hld_trcr 
 hld_trcr : rl_mmu_regs : input
Connects down to:MflipflopR_1:trcr_cntl_1:enable_l , MflipflopR_6:roll_cntl_6:enable_l , MflipflopR_1:io_lock_cntl_1:enable_l , MflipflopR_3:ptp_lock_cntl_3:enable_l , MflipflopR_1:virt_ptp2_ff_1:enable_l 
Connects up to:m_mmu_cntl:mmu_regs:hld_trcr 
 hld_trcr : rl_va_mux : output wire
Connects up to:m_mmu_cntl:va_muxl:hld_trcr 
 hld_trcr_addr : rl_mmu_regs : wire
Connects down to:MflipflopR_6:trcr_addr_ff_6:enable_l 
 hld_tt : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hld_tt 
Connects up to:Miuchip:decode:hld_tt 
 hld_tt : Mexec : input
Connects down to:Mtbr:tbr_mod:hld_tt 
Connects up to:Miuchip:exec:hld_tt 
 hld_tt : Miuchip : wire
Connects down to:Mdecode:decode:hld_tt , Mexec:exec:hld_tt 
 hld_tt : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hld_tt 
 hld_tt : Mtbr : input
Connects down to:Mflipflop_8:tt_master_8:enable_l 
Connects up to:Mexec:tbr_mod:hld_tt 
 hld_usr_msw_rf : timers : reg
 hld_wiexc : Mir : wire
Connects down to:Mflipflop_12:w_iexc_reg_12:enable_l 
 hld_wim : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hld_wim 
Connects up to:Miuchip:decode:hld_wim 
 hld_wim : Mexec : input
Connects down to:Mwim:wim_mod:hld_wim 
Connects up to:Miuchip:exec:hld_wim 
 hld_wim : Miuchip : wire
Connects down to:Mdecode:decode:hld_wim , Mexec:exec:hld_wim 
 hld_wim : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hld_wim 
 hld_wim : Mwim : input
Connects down to:Mflipflop_8:wim_master_8:enable_l 
Connects up to:Mexec:wim_mod:hld_wim 
 hld_y : Malu_control : output wire
Connects up to:Mdecode:alu_control:hld_y 
 hld_y : Mdecode : output
Connects down to:Malu_control:alu_control:hld_y 
Connects up to:Miuchip:decode:hld_y 
 hld_y : Mexec : input
Connects down to:My:y_mod:hld_y 
Connects up to:Miuchip:exec:hld_y 
 hld_y : Miuchip : wire
Connects down to:Mdecode:decode:hld_y , Mexec:exec:hld_y 
 hld_y : My : input
Connects down to:Mflipflop_32:ymaster_32:enable_l 
Connects up to:Mexec:y_mod:hld_y 
 hnoptrap_into_ex : Mir_control : wire
 hnop_into_ex : Mdecode : wire
Connects down to:Mpipec_br_vald:pipec_br_vald:hnop_into_ex , Mir_control:ir_control:hnop_into_ex , Mspecial_reg_control:special_reg_control:hnop_into_ex , Mpc_cntl:pc_cntl:hnop_into_ex , Mir:ir:hnop_into_ex 
 hnop_into_ex : Mir : input
Connects up to:Mdecode:ir:hnop_into_ex 
 hnop_into_ex : Mir_control : input
Connects up to:Mdecode:ir_control:hnop_into_ex 
 hnop_into_ex : Mpc_cntl : input
Connects up to:Mdecode:pc_cntl:hnop_into_ex 
 hnop_into_ex : Mpipec_br_vald : output
Connects up to:Mdecode:pipec_br_vald:hnop_into_ex 
 hnop_into_ex : Mspecial_reg_control : input
Connects up to:Mdecode:special_reg_control:hnop_into_ex 
 hnop_to_w : Mir : wire
 hold : CAM_LINE : input
Connects down to:MflipflopR_1:cam_line_v_1:enable_l , Mflipflop_h_32:cam_line_0_31:enable_l , Mflipflop_h_9:cam_line_32_40:enable_l 
Connects up to:cam:tag00:tag_hld , cam:tag01:tag_hld , cam:tag02:tag_hld , cam:tag03:tag_hld , cam:tag04:tag_hld , cam:tag05:tag_hld , cam:tag06:tag_hld , cam:tag07:tag_hld , cam:tag08:tag_hld , cam:tag09:tag_hld , cam:tag10:tag_hld , cam:tag11:tag_hld , cam:tag12:tag_hld , cam:tag13:tag_hld , cam:tag14:tag_hld , cam:tag15:tag_hld , cam:tag16:tag_hld , cam:tag17:tag_hld , cam:tag18:tag_hld , cam:tag19:tag_hld , cam:tag20:tag_hld , cam:tag21:tag_hld , cam:tag22:tag_hld , cam:tag23:tag_hld , cam:tag24:tag_hld , cam:tag25:tag_hld , cam:tag26:tag_hld , cam:tag27:tag_hld , cam:tag28:tag_hld , cam:tag29:tag_hld , cam:tag30:tag_hld , cam:tag31:tag_hld 
 hold : IOCAM_LINE : input
Connects down to:MflipflopR_1:cam_line_v_1:enable_l , Mflipflop_h_32:cam_line_0_31:enable_l , Mflipflop_h_9:cam_line_32_40:enable_l 
Connects up to:iocam:tag00:tag_hld , iocam:tag01:tag_hld , iocam:tag02:tag_hld , iocam:tag03:tag_hld , iocam:tag04:tag_hld , iocam:tag05:tag_hld , iocam:tag06:tag_hld , iocam:tag07:tag_hld , iocam:tag08:tag_hld , iocam:tag09:tag_hld , iocam:tag10:tag_hld , iocam:tag11:tag_hld , iocam:tag12:tag_hld , iocam:tag13:tag_hld , iocam:tag14:tag_hld , iocam:tag15:tag_hld 
 hold : Malu_control : input
Connects down to:Mflipflop_1:ex_muls_ms_1:enable_l , Mflipflop_1:nymsb_ff_1:enable_l , Mflipflop_1:alu_and_ff_1:enable_l , Mflipflop_1:alu_xnor_ff_1:enable_l , Mflipflop_1:alu_add_ff_1:enable_l , Mflipflop_1:alu_sub_ff_1:enable_l , Mflipflop_1:ycarry_in_reg_1:enable_l , Mflipflop_1:alu_tag_ff_1:enable_l , Mflipflop_1:pofs2_reg_1:enable_l , Mflipflop_1:rs1_clear_almost_reg_1:enable_l , Mflipflop_1:rs1_double_reg_1:enable_l , Mflipflop_1:rs1_negate_imul_reg_1:enable_l , Mflipflop_1:rs1_negate_idiv_reg_1:enable_l , Mflipflop_1:phelp_ctr5_reg_1:enable_l , Mflipflop_1:dvd_z_reg_1:enable_l , Mflipflop_1:psgnA_reg_1:enable_l , Mflipflop_1:psgnB_reg_1:enable_l , Mflipflop_1:force_neg_reg_1:enable_l , Mflipflop_1:force_pos_reg_1:enable_l , Mflipflop_1:not_rs_from_alu_reg_1:enable_l , Mflipflop_1:sra_ff_1:enable_l , Mflipflop_1:sll_ff_1:enable_l , Mflipflop_1:rsfsh_ff_1:enable_l , Mflipflop_1:rsfalu_ff_1:enable_l 
Connects up to:Mdecode:alu_control:hold 
 hold : Mcc : input
Connects down to:Mflipflop_4:cc_master_4:enable_l , Mflipflop_4:cc_shadow_4:enable_l 
Connects up to:Mpsr:cc_mod:hold 
 hold : Mcomplete : input
Connects up to:Mtask:complete:hold 
 hold : Mcwp : input
Connects down to:Mflipflop_3:cwp_master_3:enable_l , Mflipflop_3:cwp_shadow_reg_3:enable_l , Mflipflop_3:ecwp_master_3:enable_l , Mflipflop_3:wcwp_reg_3:enable_l 
Connects up to:Mpsr:cwp_mod:hold 
 hold : Mdata_byp1_1 : input
Connects down to:Mflipflop_1:no_bypass1_reg_1:enable_l , Mflipflop_1:byp_res3_reg_1:enable_l 
Connects up to:Mdecode:data_byp1_1:hold 
 hold : Mdata_byp1_2 : input
Connects down to:Mflipflop_1:byp_wr3_reg_1:enable_l , Mflipflop_1:byp_rf3_reg_1:enable_l 
Connects up to:Mdecode:data_byp1_2:hold 
 hold : Mdata_byp2 : input
Connects down to:Mflipflop_1:e_load_ff_1:enable_l , Mflipflop_1:w_load_ff_1:enable_l , Mflipflop_1:w_ldd_ff_1:enable_l , Mflipflop_1:e_hldd_ff_1:enable_l , Mflipflop_1:w_hldd_ff_1:enable_l 
Connects up to:Mdecode:data_byp2:hold 
 hold : Mdata_rf : input
Connects down to:Mflipflop_1:e_no_write_reg_1:enable_l , Mflipflop_1:w_no_write_reg_1:enable_l , Mflipflop_1:r_no_write_reg_1:enable_l 
Connects up to:Mdecode:data_rf:hold 
 hold : Mdcache_control : input
Connects down to:Mflipflop_1:ld_op_e_op_reg_1:enable_l , Mflipflop_1:sgnd_ld_e_op_reg_1:enable_l , Mflipflop_1:st_op_e_op_reg_1:enable_l , Mflipflop_1:fpu_mem_e_op_reg_1:enable_l , Mflipflop_1:iu_iflush_e_op_reg_1:enable_l , Mflipflop_2:size_e_reg_2:enable_l , Mflipflop_1:sel_byte_reg_1:enable_l , Mflipflop_1:sel_half_reg_1:enable_l 
Connects up to:Mdecode:dcache_control:hold 
 hold : Mdcc_bp : wire
Connects down to:Mflipflop:tf_reg:enable_l , Mflipflop_h_32:efis_reg:enable_l , Mflipflop_h_32:ds_reg:enable_l , Mflipflop_h_32:es_reg:enable_l , Mflipflop_h_32:ws_reg:enable_l , Mflipflop_h_32:rs_reg:enable_l , Mflipflop_rh:trap_ff:enable_l 
 hold : Mdecode : input wire
Connects down to:Mpipec_im_id:pipec_im_id:hold , Mpipec_br_vald:pipec_br_vald:hold , Mpipec_help_ilock:pipec_help_ilock:hold , Mir_control:ir_control:hold , Mdata_rf:data_rf:hold , Mdata_byp1_1:data_byp1_1:hold , Mdata_byp1_2:data_byp1_2:hold , Md_r_reg_cmp:d_r_reg_cmp:hold , Mdata_byp2:data_byp2:hold , Malu_control:alu_control:hold , Mpc_control:pc_control:hold , Mspecial_reg_control:special_reg_control:hold , Mdcache_control:dcache_control:hold , Mtrap_detection:trap_detection:hold , Mtrap_control:trap_control:hold , Mpc_cntl:pc_cntl:hold , Minterface:interface:hold , Mir:ir:hold , Mflipflop_1:fpins_reg_1:enable_l 
Connects up to:Miuchip:decode:hold_Mdecode 
 hold : Md_r_reg_cmp : input
Connects down to:Mflipflop_3:rcwpm_reg_3:enable_l , Mflipflop_3:rcwpm_p1_reg_3:enable_l , Mflipflop_3:rcwpm_m1_reg_3:enable_l , Mflipflop_5:r_rd_reg_5:enable_l 
Connects up to:Mdecode:d_r_reg_cmp:hold 
 hold : Met : input
Connects down to:Mflipflop_1:et_master_1:enable_l 
Connects up to:Mpsr:et_mod:hold 
 hold : ME_FREGA_2_32 : input
 hold : ME_FREGA_2_4 : input
 hold : ME_FREGA_2_55 : wire
Connects down to:ME_O2A1:iu_hold_gate_1:z , Mflipflop_32:f0:enable_l , Mflipflop_8:f1:enable_l , Mflipflop_8:f2:enable_l , Mflipflop_4:f3:enable_l , Mflipflop_3:f4:enable_l 
 hold : Mhold_control : output wire
Connects down to:Mflipflop_1:raop_reg_1:enable_l 
Connects up to:Miuchip:hold_control:hold 
 hold : Minterface : input
Connects down to:Mflipflop_4:irl_reg4_4:enable_l , Mflipflop_4:pirl_reg4_4:enable_l 
Connects up to:Mdecode:interface:hold 
 hold : Mir : input
Connects down to:Mflipflop_3:cwpm_l_reg_3:enable_l , Mflipflop_8:lbrs3_d_xl_reg_8:enable_l , Mflipflop_6:e_asim_all_reg_6:enable_l , Mflipflop_4:e_rdm_reg_4:enable_l , Mflipflop_1:e_rd0_r_reg_1:enable_l , Mflipflop_2:eir_op_mas_2:enable_l , Mflipflop_6:eir_op3_mas_6:enable_l , Mflipflop_12:e_iexc_reg_12:enable_l , Mflipflop_2:w_op_reg_2:enable_l , Mflipflop_5:w_rdm_reg_5:enable_l , Mflipflop_6:w_op3_reg_6:enable_l , Mflipflop_6:w_asim_reg_6:enable_l , Mflipflop_8:r_rdp_reg_8:enable_l , Mflipflop_15:rir_mas_15:enable_l 
Connects up to:Mdecode:ir:hold 
 hold : Mir_control : input
Connects down to:Mflipflop_3:d_hhn_reg_3:enable_l , Mflipflop_1:d_hhn2_dummy_reg_1:enable_l , Mflipflop_3:e_hhn_master_3:enable_l , Mflipflop_3:w_hhn_reg_3:enable_l , Mflipflop_3:r_hhn_reg_3:enable_l 
Connects up to:Mdecode:ir_control:hold 
 hold : Miuchip : wire
Connects down to:Mqueue:queue:hold , Mpc:pc:hold , Mhold_control:hold_control:hold 
 hold : Mpc : input
Connects down to:Mflipflop_30:p_fpc_reg_30:enable_l , Mflipflop_30:dpc_register_30:enable_l , Mflipflop_30:epc_register_30:enable_l , Mflipflop_30:wpc_register_30:enable_l , Mflipflop_30:tpc_register_30:enable_l 
Connects up to:Miuchip:pc:hold 
 hold : Mpc_cntl : input
Connects down to:Mflipflop_1:br_fbr_in_e_reg_1:enable_l , Mflipflop_1:call_in_e_reg_1:enable_l , Mflipflop_1:jmp_in_e_reg_1:enable_l , Mflipflop_1:rett_in_e_reg_1:enable_l , Mflipflop_1:wrspec_in_e_reg_1:enable_l , Mflipflop_1:wrspec_in_w_reg_1:enable_l , Mflipflop_1:cf_pterms1_reg_1:enable_l , Mflipflop_1:cf_pterms2_reg_1:enable_l , Mflipflop_1:last_cf_reg_1:enable_l , Mflipflop_1:f_in_e_reg_1:enable_l , Mflipflop_1:mult_fold_d_reg_1:enable_l , Mflipflop_1:fold_annul_reg_1:enable_l , Mflipflop_1:fold_annul_reg_2:enable_l , Mflipflop_1:fold_annul_reg_3:enable_l , Mflipflop_1:fold_annul_reg_4:enable_l , Mflipflop_1:fold_annul_reg_5:enable_l , Mflipflop_1:fold_annul_reg_6:enable_l , Mflipflop_1:fold_annul_reg_7:enable_l , Mflipflop_1:last_taken_reg_1:enable_l , Mflipflop_1:sel_pr_reg_1:enable_l , Mflipflop_1:last_null_fetch_reg_1:enable_l , Mflipflop_1:cant_unload_reg_1:enable_l , Mflipflop_1:selpfpc_t1_reg_1:enable_l , Mflipflop_1:selpfpc_t2_reg_1:enable_l , Mflipflop_1:ltafpc_t1_reg_1:enable_l , Mflipflop_1:ltafpc_t2_reg_1:enable_l , Mflipflop_1:dpc_low_reg_1:enable_l , Mflipflop_1:pfpc_low_reg_1:enable_l , Mflipflop_1:sv_rest_in_e_reg_1:enable_l , Mflipflop_1:untaken_emt_il_reg_1:enable_l , Mflipflop_1:kill_fetch_fill_reg_1:enable_l , Mflipflop_1:last_misp_reg_1:enable_l , Mflipflop_1:fwdwpda_reg_1:enable_l , Mflipflop_1:trap_bf_fold_reg_1:enable_l , Mflipflop_1:fchic_t0_reg_1:enable_l , Mflipflop_1:fchic_t1_reg_1:enable_l , Mflipflop_1:fchic_t2_reg_1:enable_l , Mflipflop_1:keep_alt_reg_1:enable_l , Mflipflop_1:kill_jmp_ld_reg_1:enable_l , Mflipflop_1:kill_ilock_br_fetch_reg_1:enable_l , Mflipflop_1:wo_wu_trap_r_reg_1:enable_l , Mflipflop_1:flshq_t1_reg_1:enable_l , Mflipflop_1:flshq_t2_reg_1:enable_l , Mflipflop_5:q_state_reg_5:enable_l , Mflipflop_1:ANNUL_am_reg2_1:enable_l , Mflipflop_1:flush_asi_w_reg_1:enable_l , Mflipflop_1:hld_llc_reg_1:enable_l , Mflipflop_1:seq_f_reg_1:enable_l 
Connects up to:Mdecode:pc_cntl:hold 
 hold : Mpc_control : input
Connects down to:Mflipflop_1:trap_adr_reg_1:enable_l , Mflipflop_1:sadr_zero_reg_1:enable_l , Mflipflop_1:e_call_reg_1:enable_l 
Connects up to:Mdecode:pc_control:hold 
 hold : Mpipec_br_vald : input
Connects down to:Mflipflop_1:annul_reg_1:enable_l 
Connects up to:Mdecode:pipec_br_vald:hold 
 hold : Mpipec_help_ilock : input
Connects down to:Mflipflop_6:help_ctr_reg_6:enable_l , Mflipflop_1:pgenhelp_ff_1:enable_l , Mflipflop_1:iu_fetch_d_reg_1:enable_l , Mflipflop_1:e_ldf_reg_1:enable_l , Mflipflop_1:e_ldfsr_stdfq_reg_1:enable_l , Mflipflop_1:d_nop_reg_1:enable_l 
Connects up to:Mdecode:pipec_help_ilock:hold 
 hold : Mpipec_im_id : input
Connects down to:Mflipflop_1:ehop3_imulbasic_reg_1:enable_l , Mflipflop_1:ehop3_idivbasic_reg_1:enable_l , Mflipflop_1:eopc_himul0_reg_1:enable_l 
Connects up to:Mdecode:pipec_im_id:hold 
 hold : Mps : input
Connects down to:Mflipflop_1:ps_master_1:enable_l 
Connects up to:Mpsr:ps_mod:hold 
 hold : Mpsr : input
Connects down to:Mcwp:cwp_mod:hold , Met:et_mod:hold , Mps:ps_mod:hold , Ms:s_mod:hold , Mflipflop_4:pil_master_4:enable_l , Mflipflop_1:ef_master_1:enable_l , Mflipflop_1:ec_master_1:enable_l , Mflipflop_1:de_master_1:enable_l , Mflipflop_1:de_sup_master_1:enable_l , Mcc:cc_mod:hold 
Connects up to:Mexec:psr_mod:hold_Mexec1 
 hold : Mqueue : input
Connects down to:Mflipflop_1:cant_unload_reg_1:enable_l 
Connects up to:Miuchip:queue:hold 
 hold : Mregfile : input
Connects down to:Mflipflop_32:rfwrdata_reg_32:enable_l , Mflipflop_8:r_rdpm_reg_8:enable_l , Mflipflop_3:cwpm__reg_3:enable_l , Mflipflop_8:rs3_phys_reg_8:enable_l , Mflipflop_1:word_st_e_reg_1:enable_l , Mflipflop_1:half_st_e_reg_1:enable_l , Mflipflop_1:byte_st_e_reg_1:enable_l , Mflipflop_1:rfwer_reg_1:enable_l 
Connects up to:Miuchip:regfile:hold_Mregfile 
 hold : Ms : input
Connects down to:Mflipflop_1:s_master_1:enable_l 
Connects up to:Mpsr:s_mod:hold 
 hold : Mspecial_reg_control : input
Connects down to:Mflipflop_1:rdtpc_m_1:enable_l , Mflipflop_1:e_rdpsr_op_reg_1:enable_l , Mflipflop_1:e_rdpsr_m_1:enable_l , Mflipflop_1:e_rdwim_op_reg_1:enable_l , Mflipflop_1:e_rdwim_m_1:enable_l , Mflipflop_1:e_rdy_op_forilock_reg_1:enable_l , Mflipflop_1:e_rdy_m_1:enable_l , Mflipflop_1:e_rdtbr_op_reg_1:enable_l , Mflipflop_1:e_rdtbr_m_1:enable_l , Mflipflop_1:e_jmpcall_m_1:enable_l , Mflipflop_1:sel_pcspec_l_reg_1:enable_l , Mflipflop_1:setcc_ff_1:enable_l , Mflipflop_1:wsetcc_reg_1:enable_l , Mflipflop_1:alternate_e_reg_1:enable_l 
Connects up to:Mdecode:special_reg_control:hold 
 hold : Mtask : wire
Connects down to:Mflipflop_noop:hold_ff:in , Mcomplete:complete:hold , Mtrace:trace:hold 
 hold : Mtbr : input
Connects down to:Mflipflop_20:tba_master_20:enable_l , Mflipflop_8:tt_master_8:enable_l 
Connects up to:Mexec:tbr_mod:hold_Mexec1 
 hold : Mtrace : input
Connects up to:Mtask:trace:hold 
 hold : Mtrapcode : input
Connects up to:Mtrap_control:trapcode_mod:hold 
 hold : Mtrapw_int : input
Connects down to:Mflipflop_1:trapw_int_val_reg_1:enable_l , Mflipflop_1:p_et_reg_1:enable_l 
Connects up to:Mtrap_detection:trapw_int_mod:hold 
 hold : Mtrap_control : input
Connects down to:Mflipflop_1:d_traps_ff_1:enable_l , Mflipflop_1:e_traps_ff_1:enable_l , Mflipflop_1:trap_1_ff_1:enable_l , Mflipflop_1:trap_2_ff_1:enable_l , Mflipflop_1:d_trap_mas_1:enable_l , Mflipflop_7:de_trap_reg_7:enable_l , Mflipflop_7:dw_trap_reg_7:enable_l , Mflipflop_7:ew_trap_reg_7:enable_l , Mtrapcode:trapcode_mod:hold 
Connects up to:Mdecode:trap_control:hold 
 hold : Mtrap_detection : input
Connects down to:Mflipflop_1:nnerror_mode_reg_1:enable_l , Mflipflop_1:nerror_mode_reg_1:enable_l , Mflipflop_1:error_mode_reg_1:enable_l , Mflipflop_1:iu_event_w_reg_1:enable_l , Mflipflop_1:pbicc_taken_reg_1:enable_l , Mflipflop_1:wfpi_ff_1:enable_l , Mflipflop_1:w_tagcctv_reg_1:enable_l , Mflipflop_1:no_ints_ff_1:enable_l , Mflipflop_1:r_wrpsr_reg_1:enable_l , Mtrapw_int:trapw_int_mod:hold 
Connects up to:Mdecode:trap_detection:hold 
 hold : Mwim : input
Connects down to:Mflipflop_8:wim_master_8:enable_l 
Connects up to:Mexec:wim_mod:hold_Mexec1 
 hold : My : input
Connects down to:Mflipflop_32:ymaster_32:enable_l 
Connects up to:Mexec:y_mod:hold_Mexec1 
 hold : rsflop : input
Connects down to:ASFFRHA:dff:H 
Connects up to:rl_mmu_regs:data_err_ff:hold_sfsr , rsflop_mfsr:mfsr_ff07:hold , rsflop_mfsr:mfsr_ff06:hold , rsflop_mfsr:mfsr_ff05:hold , rsflop_mfsr:mfsr_ff04:hold , rsflop_mfsr:mfsr_ff03:hold , rsflop_mfsr:mfsr_ff02:hold , rsflop_mfsr:mfsr_ff01:hold , rsflop_mfsr:mfsr_ff00:hold , rsflop_sfsr:sfsr_ff14:hold , rsflop_sfsr:sfsr_ff13:hold , rsflop_sfsr:sfsr_ff12:hold , rsflop_sfsr:sfsr_ff11:hold , rsflop_sfsr:sfsr_ff10:hold , rsflop_sfsr:sfsr_ff09:hold , rsflop_sfsr:sfsr_ff08:hold , rsflop_sfsr:sfsr_ff07:hold , rsflop_sfsr:sfsr_ff06:hold , rsflop_sfsr:sfsr_ff05:hold , rsflop_sfsr:sfsr_ff04:hold , rsflop_sfsr:sfsr_ff03:hold , rsflop_sfsr:sfsr_ff02:hold , rsflop_sfsr:sfsr_ff01:hold , rsflop_sfsr:sfsr_ff00:hold , rsflop_afsr:afsr_ff09:hold , rsflop_afsr:afsr_ff08:hold , rsflop_afsr:afsr_ff07:hold , rsflop_afsr:afsr_ff06:hold , rsflop_afsr:afsr_ff05:hold , rsflop_afsr:afsr_ff04:hold , rsflop_afsr:afsr_ff03:hold , rsflop_afsr:afsr_ff02:hold , rsflop_afsr:afsr_ff01:hold , rsflop_afsr:afsr_ff00:hold , rsflop_merr:merr_ff03:hold , rsflop_merr:merr_ff02:hold , rsflop_merr:merr_ff01:hold , rsflop_merr:merr_ff00:hold 
 hold : rsflop_afsr : input
Connects down to:rsflop:afsr_ff09:hold , rsflop:afsr_ff08:hold , rsflop:afsr_ff07:hold , rsflop:afsr_ff06:hold , rsflop:afsr_ff05:hold , rsflop:afsr_ff04:hold , rsflop:afsr_ff03:hold , rsflop:afsr_ff02:hold , rsflop:afsr_ff01:hold , rsflop:afsr_ff00:hold 
Connects up to:rl_mmu_regs:afsr_reg:afar_lock 
 hold : rsflop_merr : input
Connects down to:rsflop:merr_ff03:hold , rsflop:merr_ff02:hold , rsflop:merr_ff01:hold , rsflop:merr_ff00:hold 
Connects up to:rl_mmu_regs:mfsr_err_reg:mfsr , rl_mmu_regs:mfsr_err_reg:mfsr_read 
 hold : rsflop_mfsr : input
Connects down to:rsflop:mfsr_ff07:hold , rsflop:mfsr_ff06:hold , rsflop:mfsr_ff05:hold , rsflop:mfsr_ff04:hold , rsflop:mfsr_ff03:hold , rsflop:mfsr_ff02:hold , rsflop:mfsr_ff01:hold , rsflop:mfsr_ff00:hold 
Connects up to:rl_mmu_regs:mfsr_reg:mfsr_hld 
 hold : rsflop_sfsr : input
Connects down to:rsflop:sfsr_ff14:hold , rsflop:sfsr_ff13:hold , rsflop:sfsr_ff12:hold , rsflop:sfsr_ff11:hold , rsflop:sfsr_ff10:hold , rsflop:sfsr_ff09:hold , rsflop:sfsr_ff08:hold , rsflop:sfsr_ff07:hold , rsflop:sfsr_ff06:hold , rsflop:sfsr_ff05:hold , rsflop:sfsr_ff04:hold , rsflop:sfsr_ff03:hold , rsflop:sfsr_ff02:hold , rsflop:sfsr_ff01:hold , rsflop:sfsr_ff00:hold 
Connects up to:rl_mmu_regs:sfsr_reg:hold_sfsr 
 hold1 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g1:O , JBUFD:arthur_hc_b3:A , JBUFD:arthur_hc_b4:A 
 hold2 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g2:O 
 hold3 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g3:O , JBUFD:arthur_hc_b5:A 
 hold4 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g4:O , JINVD:arthur_hc_i1:A 
 hold5 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g5:O , JBUFD:arthur_hc_b1:A 
 hold6 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g6:O , JBUFD:arthur_hc_b2:A 
 hold_4_0 : stat_ctl : wire
Connects down to:ME_AI22O1_C_5:iu_hold_gate_12:a2 , ME_AI22O1_C_5:iu_hold_gate_12:b2 , ME_AI22O1_C_5:iu_hold_gate_13:a2 , ME_AI22O1_C_5:iu_hold_gate_13:b2 , ME_AI22O1_C_2:iu_hold_gate_14:a2 , ME_AI22O1_C_2:iu_hold_gate_14:b2 
 hold_after_last_stream : dwait : input
Connects up to:rl_dc_cntl:dwait:hold_after_last_stream 
 hold_after_last_stream : rl_dc_cntl : wire
Connects down to:Mflipflop_r:hold_after_last_stream_ff:out , dwait:dwait:hold_after_last_stream 
 hold_alt : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:ais_reg:enable_l 
 hold_alt : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hold_alt 
Connects up to:Miuchip:decode:hold_alt 
 hold_alt : Miuchip : wire
Connects down to:Mqueue:queue:hold_alt , Mdecode:decode:hold_alt 
 hold_alt : Mpc_cntl : output wire
Connects down to:Mflipflop_1:alttag_low_reg_1:enable_l 
Connects up to:Mdecode:pc_cntl:hold_alt 
 hold_alt : Mqueue : input
Connects down to:Mflipflop_32:alt_reg_32:enable_l , Mflipflop_11:alt_iexc_reg_11:enable_l , Mflipflop_30:alt_t_reg_30:enable_l 
Connects up to:Miuchip:queue:hold_alt 
 hold_br1 : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:dfis_reg:enable_l 
 hold_br1 : Mpc_cntl : wire
Connects down to:Mflipflop_4:dbr_cond_reg_4:enable_l , Mflipflop_1:dbr_annul_reg_1:enable_l , Mflipflop_1:f_in_d_reg_1:enable_l , Mflipflop_1:misp_reg_1:enable_l 
 hold_cc : Mcc : input
Connects up to:Mpsr:cc_mod:hold_cc 
 hold_cc : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hold_cc 
Connects up to:Miuchip:decode:hold_cc 
 hold_cc : Mexec : input
Connects down to:Mpsr:psr_mod:hold_cc 
Connects up to:Miuchip:exec:hold_cc 
 hold_cc : Miuchip : wire
Connects down to:Mdecode:decode:hold_cc , Mexec:exec:hold_cc 
 hold_cc : Mpsr : input
Connects down to:Mcc:cc_mod:hold_cc 
Connects up to:Mexec:psr_mod:hold_cc 
 hold_cc : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hold_cc 
 hold_count : misc : wire
Connects down to:rl_clk_stop:clk_stop:hold_count , rl_cyc_ctr:cyc_ctr:hold_count 
 hold_count : rl_clk_stop : output wire
Connects down to:Mflipflop_srh:ext_ev1_ff:enable_l , Mflipflop_srh:ext_ev2_ff:enable_l 
Connects up to:misc:clk_stop:hold_count 
 hold_count : rl_cyc_ctr : input
Connects down to:Mflipflop_rh_32:cc_reg:enable_l , Mflipflop_rh:ovfl_ff:enable_l 
Connects up to:misc:cyc_ctr:hold_count 
 hold_count_cycle : rl_clk_stop : wire
 hold_cyc : abort_write_sm : input
Connects up to:afxmaster:aw_sm:hold_cyc 
 hold_cyc : afxmaster : wire
Connects down to:abort_write_sm:aw_sm:hold_cyc , afxm_sm:afxm_sm1:hold_cyc 
 hold_cyc : afxm_sm : output wire
Connects up to:afxmaster:afxm_sm1:hold_cyc 
 hold_cyc1 : afxmaster : wire
Connects down to:afxm_sm:afxm_sm1:hold_cyc1 
 hold_cyc1 : afxm_sm : output reg
Connects up to:afxmaster:afxm_sm1:hold_cyc1 
 hold_d : fp_qst : wire
Connects down to:ME_OR2_B:iu_hold_gate_1:z , ME_OR2_B:iu_hold_gate_2:z , ME_OR2_B:iu_hold_gate_3:z , ME_OR2_B:iu_hold_gate_4:z , ME_FREG_H_32:ir_reg_d:H 
 hold_d1 : Mtask : wire
Connects down to:Mflipflop_noop:hold_ff:out 
 hold_din : fp_rf : input
Connects up to:fpufpc:fprf:fprf_hold_din 
 hold_divovf : Malu_control : wire
Connects down to:Mflipflop_1:det_divovf_reg_1:enable_l 
 hold_dvnd_sgn : Malu_control : wire
Connects down to:Mflipflop_1:dvnd_sgn_reg_1:enable_l , Mflipflop_1:final_sgn_reg_1:enable_l 
 hold_ets : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hold_ets 
Connects up to:Miuchip:decode:hold_ets 
 hold_ets : Mexec : input
Connects up to:Miuchip:exec:hold_ets 
 hold_ets : Miuchip : wire
Connects down to:Mdecode:decode:hold_ets , Mexec:exec:hold_ets 
 hold_ets : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hold_ets 
 hold_ets_sm : Met : input
Connects up to:Mpsr:et_mod:hold_ets_sm 
 hold_ets_sm : Mexec : wire
Connects down to:Mpsr:psr_mod:hold_ets_sm 
 hold_ets_sm : Mpsr : input
Connects down to:Met:et_mod:hold_ets_sm , Ms:s_mod:hold_ets_sm 
Connects up to:Mexec:psr_mod:hold_ets_sm 
 hold_ets_sm : Ms : input
Connects up to:Mpsr:s_mod:hold_ets_sm 
 hold_fetch_f_l : mmu : input
Connects down to:m_mmu_cntl:MMU_cntl:hold_fetch_f_l 
Connects up to:ssparc_core:ssparc_mmu:hold_fetch_f_l 
 hold_fetch_f_l : m_mmu_cntl : input
Connects down to:rl_mmu_regs:mmu_regs:hold_fetch_f_l 
Connects up to:mmu:MMU_cntl:hold_fetch_f_l 
 hold_fetch_f_l : rl_cc : output
Connects down to:rl_ic_cntl:ic_cntl:hold_fetch_f_l 
Connects up to:ssparc_core:cc:hold_fetch_f_l 
 hold_fetch_f_l : rl_ic_cntl : output wire
Connects up to:rl_cc:ic_cntl:hold_fetch_f_l 
 hold_fetch_f_l : rl_mmu_regs : input
Connects down to:Mflipflop_r_1:hold_fetch_f_1:din 
Connects up to:m_mmu_cntl:mmu_regs:hold_fetch_f_l 
 hold_fetch_f_l : ssparc_core : wire
Connects down to:mmu:ssparc_mmu:hold_fetch_f_l , rl_cc:cc:hold_fetch_f_l 
 hold_ic : Mdecode : input
Connects down to:Mpc_cntl:pc_cntl:hold_ic 
Connects up to:Miuchip:decode:hold_ic 
 hold_ic : Mhold_control : output wire
Connects down to:Mflipflop_1:ihold_d1_reg_1:din 
Connects up to:Miuchip:hold_control:hold_ic 
 hold_ic : Miuchip : wire
Connects down to:Mpc:pc:hold_ic , Mdecode:decode:hold_ic , Mhold_control:hold_control:hold_ic 
 hold_ic : Mpc : input
Connects up to:Miuchip:pc:hold_ic 
 hold_ic : Mpc_cntl : input
Connects up to:Mdecode:pc_cntl:hold_ic 
 hold_int_event : rl_clk_stop : wire
Connects down to:Mflipflop_srh:int_ev_ff:enable_l 
 hold_Mdecode : Mhold_control : output wire
Connects up to:Miuchip:hold_control:hold_Mdecode 
 hold_Mdecode : Miuchip : wire
Connects down to:Mdecode:decode:hold , Mhold_control:hold_control:hold_Mdecode 
 hold_Mexec1 : Mexec : input
Connects down to:Mflipflop_1:e_mulsm_reg_1:enable_l , Mflipflop_1:rs1_negate_reg_1:enable_l , Mflipflop_1:rs1_negate_l_reg_1:enable_l , Mflipflop_1:e_not_negmul_reg_1:enable_l , Mflipflop_1:sel_w_mult_reg_1:enable_l , Mflipflop_1:sel_w_mult_l_b_reg_1:enable_l , Mflipflop_1:sel_w_mult_l_not_b_reg_1:enable_l , Mflipflop_1:shiftin_a_reg_1:enable_l , Mflipflop_32:alu_s1_reg_32:enable_l , Mflipflop_2:alu_s1_high_reg_2:enable_l , Mflipflop_2:ext_bits_reg_2:enable_l , Mpsr:psr_mod:hold , Mwim:wim_mod:hold , Mtbr:tbr_mod:hold , My:y_mod:hold 
Connects up to:Miuchip:exec:hold_Mexec1 
 hold_Mexec1 : Mhold_control : output
Connects down to:JBUFD:arthur_hc_b2:O 
Connects up to:Miuchip:hold_control:hold_Mexec1 
 hold_Mexec1 : Miuchip : wire
Connects down to:Mhold_control:hold_control:hold_Mexec1 , Mexec:exec:hold_Mexec1 
 hold_Mexec2 : Mexec : input
Connects up to:Miuchip:exec:hold_Mexec2 
 hold_Mexec2 : Mhold_control : output
Connects down to:JBUFD:arthur_hc_b3:O 
Connects up to:Miuchip:hold_control:hold_Mexec2 
 hold_Mexec2 : Miuchip : wire
Connects down to:Mhold_control:hold_control:hold_Mexec2 , Mexec:exec:hold_Mexec2 
 hold_Mexec3 : Mexec : input
Connects up to:Miuchip:exec:hold_Mexec3 
 hold_Mexec3 : Mhold_control : output
Connects down to:JBUFD:arthur_hc_b4:O 
Connects up to:Miuchip:hold_control:hold_Mexec3 
 hold_Mexec3 : Miuchip : wire
Connects down to:Mhold_control:hold_control:hold_Mexec3 , Mexec:exec:hold_Mexec3 
 hold_Mregfile : Mhold_control : output wire
Connects up to:Miuchip:hold_control:hold_Mregfile 
 hold_Mregfile : Miuchip : wire
Connects down to:Mhold_control:hold_control:hold_Mregfile , Mregfile:regfile:hold 
 hold_noic : Mdecode : input
Connects down to:Mpc_cntl:pc_cntl:hold_noic 
Connects up to:Miuchip:decode:hold_noic 
 hold_noic : Mhold_control : output wire
Connects up to:Miuchip:hold_control:hold_noic 
 hold_noic : Miuchip : wire
Connects down to:Mdecode:decode:hold_noic , Mhold_control:hold_control:hold_noic 
 hold_noic : Mpc_cntl : input
Connects up to:Mdecode:pc_cntl:hold_noic 
 hold_off_standby : arbiter : wire
 hold_par : dp_mmu : input
Connects down to:MflipflopR_31:par_31:enable_l 
Connects up to:mmu:MMU_dp:hold_par 
 hold_par : mmu : wire
Connects down to:m_mmu_cntl:MMU_cntl:hold_par , dp_mmu:MMU_dp:hold_par 
 hold_par : m_mmu_cntl : output
Connects down to:rl_mmu_lgc:mmu_lgc:hold_par , rl_par_cntl:par_cntl:hold_par , rl_mmu_regs:mmu_regs:hold_par 
Connects up to:mmu:MMU_cntl:hold_par 
 hold_par : rl_mmu_lgc : input
Connects down to:MflipflopR_1:io_space_ff_1:enable_l , MflipflopR_1:cntl_space_ff_1:enable_l , MflipflopR_1:mem_space_ff_1:enable_l , MflipflopR_1:fb_space_ff_1:enable_l , MflipflopR_1:pci_space_ff_1:enable_l 
Connects up to:m_mmu_cntl:mmu_lgc:hold_par 
 hold_par : rl_mmu_regs : input
Connects down to:MflipflopR_2:par_lvl_ff_2:enable_l , MflipflopR_1:par_sbit_ff_1:enable_l , MflipflopR_1:par_cbit_ff_1:enable_l 
Connects up to:m_mmu_cntl:mmu_regs:hold_par 
 hold_par : rl_par_cntl : output
Connects up to:m_mmu_cntl:par_cntl:hold_par 
 hold_pipe : Mcomplete : wire
 hold_ps : Mdecode : output
Connects down to:Mspecial_reg_control:special_reg_control:hold_ps 
Connects up to:Miuchip:decode:hold_ps 
 hold_ps : Mexec : input
Connects up to:Miuchip:exec:hold_ps 
 hold_ps : Miuchip : wire
Connects down to:Mdecode:decode:hold_ps , Mexec:exec:hold_ps 
 hold_ps : Mspecial_reg_control : output wire
Connects up to:Mdecode:special_reg_control:hold_ps 
 hold_ps_sm : Mexec : wire
Connects down to:Mpsr:psr_mod:hold_ps_sm 
 hold_ps_sm : Mps : input
Connects up to:Mpsr:ps_mod:hold_ps_sm 
 hold_ps_sm : Mpsr : input
Connects down to:Mps:ps_mod:hold_ps_sm 
Connects up to:Mexec:psr_mod:hold_ps_sm 
 hold_q1 : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hold_q1 
Connects up to:Miuchip:decode:hold_q1 
 hold_q1 : Miuchip : wire
Connects down to:Mqueue:queue:hold_q1 , Mdecode:decode:hold_q1 
 hold_q1 : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hold_q1 
 hold_q1 : Mqueue : input
Connects up to:Miuchip:queue:hold_q1 
 hold_q1_real : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:q1is_reg:enable_l 
 hold_q1_real : Mpc_cntl : wire
Connects down to:Mflipflop_10:dum_toq_reg_10:enable_l , Mflipflop_9:dum_q1_iexc_reg_9:enable_l 
 hold_q1_real : Mqueue : wire
Connects down to:Mflipflop_32:q1_reg_32:enable_l , Mflipflop_11:iexc1_reg_11:enable_l , Mflipflop_30:q1_t_reg_30:enable_l 
 hold_q2 : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hold_q2 
Connects up to:Miuchip:decode:hold_q2 
 hold_q2 : Miuchip : wire
Connects down to:Mqueue:queue:hold_q2 , Mdecode:decode:hold_q2 
 hold_q2 : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hold_q2 
 hold_q2 : Mqueue : input
Connects up to:Miuchip:queue:hold_q2 
 hold_q2_real : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:q2is_reg:enable_l 
 hold_q2_real : Mqueue : wire
Connects down to:Mflipflop_32:q2_reg_32:enable_l , Mflipflop_11:iexc2_reg_11:enable_l , Mflipflop_30:q2_t_reg_30:enable_l 
 hold_q3 : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hold_q3 
Connects up to:Miuchip:decode:hold_q3 
 hold_q3 : Miuchip : wire
Connects down to:Mqueue:queue:hold_q3 , Mdecode:decode:hold_q3 
 hold_q3 : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hold_q3 
 hold_q3 : Mqueue : input
Connects up to:Miuchip:queue:hold_q3 
 hold_q3_real : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:q3is_reg:enable_l 
 hold_q3_real : Mqueue : wire
Connects down to:Mflipflop_32:q3_reg_32:enable_l , Mflipflop_11:iexc3_reg_11:enable_l , Mflipflop_30:q3_t_reg_30:enable_l 
 hold_q4 : Mdecode : output
Connects down to:Mpc_cntl:pc_cntl:hold_q4 
Connects up to:Miuchip:decode:hold_q4 
 hold_q4 : Miuchip : wire
Connects down to:Mqueue:queue:hold_q4 , Mdecode:decode:hold_q4 
 hold_q4 : Mpc_cntl : output wire
Connects up to:Mdecode:pc_cntl:hold_q4 
 hold_q4 : Mqueue : input
Connects up to:Miuchip:queue:hold_q4 
 hold_q4_real : Mdcc_bp : wire
Connects down to:Mflipflop_h_32:q4is_reg:enable_l 
 hold_q4_real : Mqueue : wire
Connects down to:Mflipflop_32:q4_reg_32:enable_l , Mflipflop_11:iexc4_reg_11:enable_l , Mflipflop_30:q4_t_reg_30:enable_l 
 hold_rcc_clk : rl_clk_cntl : wire
 hold_rfr_clock : rl_clk_cntl : wire
 hold_rs2 : Mdata_rf : wire
 hold_sfar : m_mmu_cntl : output
Connects down to:rl_mmu_regs:mmu_regs:hold_sfar 
Connects up to:mmu:MMU_cntl:hld_sfar 
 hold_sfar : rl_mmu_regs : output
Connects up to:m_mmu_cntl:mmu_regs:hold_sfar 
 hold_sfsr : rl_mmu_regs : wire
Connects down to:rsflop:data_err_ff:hold , rsflop_sfsr:sfsr_reg:hold 
 hold_stzr : Malu_control : wire
Connects down to:Mflipflop_1:sticky_zero_reg_1:enable_l 
 hold_sysclk : rl_clk_cntl : wire
 hold_term1 : Mhold_control : wire
Connects down to:JDB122A:arthur_hc_g1:C , JDB122A:arthur_hc_g2:C , JDB122A:arthur_hc_g3:C , JDB122A:arthur_hc_g4:C , JDB122A:arthur_hc_g5:C , JDB122A:arthur_hc_g6:C 
 hold_usr_msw_shdor : timers : wire
 hold_wb_0 : writebuffer : wire
Connects down to:Mflipflop_32:write_buffer_0_hi:enable_l , Mflipflop_1:write_buffer_0:enable_l , MflipflopR:wb_0_vb:enable_l 
 hold_wb_0_lsw : writebuffer : wire
Connects down to:Mflipflop_32:write_buffer_0_lo:enable_l 
 hold_wb_1 : writebuffer : wire
Connects down to:Mflipflop_mux2_h_32:write_buffer_1_hi:enable_l , Mflipflop_mux2_h_1:write_buffer_1:enable_l , MflipflopR:wb_1_vb:enable_l 
 hold_wb_1_lsw : writebuffer : wire
Connects down to:Mflipflop_mux2_h_32:write_buffer_1_lo:enable_l 
 hold_wb_2 : writebuffer : wire
Connects down to:Mflipflop_mux2_h_32:write_buffer_2_hi:enable_l , Mflipflop_mux2_h_1:write_buffer_2:enable_l , MflipflopR:wb_2_vb:enable_l 
 hold_wb_2_lsw : writebuffer : wire
Connects down to:Mflipflop_mux2_h_32:write_buffer_2_lo:enable_l 
 hold_wb_3 : writebuffer : wire
Connects down to:Mflipflop_mux2_h_32:write_buffer_3_hi:enable_l , Mflipflop_mux2_h_1:write_buffer_3:enable_l , MflipflopR:wb_3_vb:enable_l 
 hold_wb_3_lsw : writebuffer : wire
Connects down to:Mflipflop_mux2_h_32:write_buffer_3_lo:enable_l 
 hold_Wreg : Malu_control : output wire
Connects up to:Mdecode:alu_control:hold_Wreg 
 hold_Wreg : Mdecode : output
Connects down to:Malu_control:alu_control:hold_Wreg 
Connects up to:Miuchip:decode:hold_Wreg 
 hold_Wreg : Mexec : input
Connects up to:Miuchip:exec:hold_Wreg 
 hold_Wreg : Miuchip : wire
Connects down to:Mdecode:decode:hold_Wreg , Mexec:exec:hold_Wreg 
 hold_Wreg_real : Mexec : wire
Connects down to:Mflipflop_32:result_master_32:enable_l , Mflipflop_2:result_high2_reg_2:enable_l 
 host1_async_perr : pcic : wire
Connects down to:f_afx_slave:f_afx_slave:pci_async_perror , pci_core:PCI_CORE:host1_async_perr 
 host1_complete : pcic : wire
Connects down to:f_afx_slave:f_afx_slave:pci_complete , pci_core:PCI_CORE:host1_complete 
 host1_fatal : pcic : wire
Connects down to:f_afx_slave:f_afx_slave:pci_error , pci_core:PCI_CORE:host1_fatal 
 host1_perr : pcic : wire
Connects down to:f_afx_slave:f_afx_slave:pci_perror , pci_core:PCI_CORE:host1_perr 
 host_config_access_busy : afx_slave_sm : output wire
Connects up to:f_afx_slave:afx_slave_sm:host_config_access_busy 
 host_config_access_busy : f_afx_slave : output
Connects down to:afx_slave_sm:afx_slave_sm:host_config_access_busy 
Connects up to:pcic:f_afx_slave:host_config_access_busy 
 host_config_access_busy : pcic : wire
Connects down to:f_afx_slave:f_afx_slave:host_config_access_busy , pci_core:PCI_CORE:host_config_access_busy 
 hp_rf_src1 : Mregfile : wire
Connects down to:HP136X32:rf_ram:DOA31 , HP136X32:rf_ram:DOA30 , HP136X32:rf_ram:DOA29 , HP136X32:rf_ram:DOA28 , HP136X32:rf_ram:DOA27 , HP136X32:rf_ram:DOA26 , HP136X32:rf_ram:DOA25 , HP136X32:rf_ram:DOA24 , HP136X32:rf_ram:DOA23 , HP136X32:rf_ram:DOA22 , HP136X32:rf_ram:DOA21 , HP136X32:rf_ram:DOA20 , HP136X32:rf_ram:DOA19 , HP136X32:rf_ram:DOA18 , HP136X32:rf_ram:DOA17 , HP136X32:rf_ram:DOA16 , HP136X32:rf_ram:DOA15 , HP136X32:rf_ram:DOA14 , HP136X32:rf_ram:DOA13 , HP136X32:rf_ram:DOA12 , HP136X32:rf_ram:DOA11 , HP136X32:rf_ram:DOA10 , HP136X32:rf_ram:DOA9 , HP136X32:rf_ram:DOA8 , HP136X32:rf_ram:DOA7 , HP136X32:rf_ram:DOA6 , HP136X32:rf_ram:DOA5 , HP136X32:rf_ram:DOA4 , HP136X32:rf_ram:DOA3 , HP136X32:rf_ram:DOA2 , HP136X32:rf_ram:DOA1 , HP136X32:rf_ram:DOA0 
 hp_rf_src2 : Mregfile : wire
Connects down to:HP136X32:rf_ram:DOB31 , HP136X32:rf_ram:DOB30 , HP136X32:rf_ram:DOB29 , HP136X32:rf_ram:DOB28 , HP136X32:rf_ram:DOB27 , HP136X32:rf_ram:DOB26 , HP136X32:rf_ram:DOB25 , HP136X32:rf_ram:DOB24 , HP136X32:rf_ram:DOB23 , HP136X32:rf_ram:DOB22 , HP136X32:rf_ram:DOB21 , HP136X32:rf_ram:DOB20 , HP136X32:rf_ram:DOB19 , HP136X32:rf_ram:DOB18 , HP136X32:rf_ram:DOB17 , HP136X32:rf_ram:DOB16 , HP136X32:rf_ram:DOB15 , HP136X32:rf_ram:DOB14 , HP136X32:rf_ram:DOB13 , HP136X32:rf_ram:DOB12 , HP136X32:rf_ram:DOB11 , HP136X32:rf_ram:DOB10 , HP136X32:rf_ram:DOB9 , HP136X32:rf_ram:DOB8 , HP136X32:rf_ram:DOB7 , HP136X32:rf_ram:DOB6 , HP136X32:rf_ram:DOB5 , HP136X32:rf_ram:DOB4 , HP136X32:rf_ram:DOB3 , HP136X32:rf_ram:DOB2 , HP136X32:rf_ram:DOB1 , HP136X32:rf_ram:DOB0 
 hp_rf_src3 : Mregfile : wire
Connects down to:HP136X32:rf_ram:DOC31 , HP136X32:rf_ram:DOC30 , HP136X32:rf_ram:DOC29 , HP136X32:rf_ram:DOC28 , HP136X32:rf_ram:DOC27 , HP136X32:rf_ram:DOC26 , HP136X32:rf_ram:DOC25 , HP136X32:rf_ram:DOC24 , HP136X32:rf_ram:DOC23 , HP136X32:rf_ram:DOC22 , HP136X32:rf_ram:DOC21 , HP136X32:rf_ram:DOC20 , HP136X32:rf_ram:DOC19 , HP136X32:rf_ram:DOC18 , HP136X32:rf_ram:DOC17 , HP136X32:rf_ram:DOC16 , HP136X32:rf_ram:DOC15 , HP136X32:rf_ram:DOC14 , HP136X32:rf_ram:DOC13 , HP136X32:rf_ram:DOC12 , HP136X32:rf_ram:DOC11 , HP136X32:rf_ram:DOC10 , HP136X32:rf_ram:DOC9 , HP136X32:rf_ram:DOC8 , HP136X32:rf_ram:DOC7 , HP136X32:rf_ram:DOC6 , HP136X32:rf_ram:DOC5 , HP136X32:rf_ram:DOC4 , HP136X32:rf_ram:DOC3 , HP136X32:rf_ram:DOC2 , HP136X32:rf_ram:DOC1 , HP136X32:rf_ram:DOC0 
 HR : PLL300CBFI : input
 hst_op : Miu : wire
 htrap : Mdcc_bp : reg
 htrap_into_ex : Mdecode : wire
Connects down to:Mir_control:ir_control:htrap_into_ex , Mspecial_reg_control:special_reg_control:htrap_into_ex , Mir:ir:htrap_into_ex 
 htrap_into_ex : Mir : input
Connects up to:Mdecode:ir:htrap_into_ex 
 htrap_into_ex : Mir_control : input
Connects up to:Mdecode:ir_control:htrap_into_ex 
 htrap_into_ex : Mspecial_reg_control : input
Connects up to:Mdecode:special_reg_control:htrap_into_ex 
 hw_int : interrupts : wire
 hw_irl : interrupts : wire
 hw_lvl_15_int : interrupts : wire
Connects down to:sync:sync_pci11:in 
 hw_w : herbulator : wire
 hzz : Msystem : wire
Connects down to:pcimaster:lmc_master1:syncin 
 h_pci_int : interrupts : wire
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