/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)alu.v
***
***
****************************************************************************
****************************************************************************/
// @(#)alu.v	1.8 3/12/93
// alu.v
//------------------------------------------------------------------------------
/*
	This file contains module Malu, which models the
	guts of the ALU and module Mccgen which models
	condition code generation.

	In addition, it now has the wrapper Malucc called
	from Mexec.
*/


module Malu (alu_out, carry_32, carry_31,
	alu_s1s, alu_s2i, carry_in,
	alu_ADD, alu_AND, alu_XNOR);

// OUTPUTS

output [31:0] alu_out;		// combinational ALU result
output carry_32;		// The 32nd bit of the result (carry out)
output carry_31;		// The carry into the last bit
				// (used to calculate overflow)

// INPUTS

input [31:0] alu_s1s;		// input data source 1 possibly shifted for muls
input [31:0] alu_s2i;		// input data source 2 possibly inverted
input carry_in;			// input carry

// CONTROL

input alu_ADD;			// control tells the alu to add
input alu_AND;			// control tells the alu to and
input alu_XNOR;			// control tells the alu to xnor

	reg [31:0] alu_out;
	reg carry_32, carry_31;

	always @ (alu_s1s or alu_s2i or carry_in or
		alu_ADD or alu_AND or alu_XNOR) begin

		carry_31 = 0;	// default
		carry_32 = 0;

		case({alu_ADD, alu_XNOR, alu_AND})

		3'b100,
		3'b101,
		3'b110,
		3'b111: // ADD
		begin
			{carry_32, alu_out} = alu_s1s + alu_s2i + carry_in;
			carry_31 = (alu_s1s[31] ^ alu_s2i[31]) ^ alu_out[31];
		end

		3'b001: // AND
				alu_out = alu_s1s & alu_s2i;
			
		3'b000: // ORN
				alu_out = alu_s1s | ~alu_s2i;
			
		3'b010: // XNOR
				alu_out = ~(alu_s1s ^ alu_s2i);
		
		3'b011: // PASS
				alu_out = alu_s1s;

// synopsys translate_off
		default: begin // otherwise
				alu_out = 32'hx;
				carry_32 = 'bx;
				carry_31 = 'bx;
			end
// synopsys translate_on
		endcase
	end
endmodule


module Mccgen (alu_cc,
	alu_out, carry_32, carry_31,
	alu_sub, tagged_ovf
	);

// OUTPUT

output [3:0] alu_cc;		// new CC's {N,Z,V,C}

// INPUTS

input [31:0] alu_out;		// alu output result
input carry_32, carry_31;	// alu carries

input alu_sub;			// indicates a subtract (invert C out)
input tagged_ovf;		// tagged ovf detected in control logic

	wire N = alu_out[31];
	wire Z = alu_out == 32'b0;
	wire C = carry_32 ^ alu_sub;	// 68000 compatibility

//   tagged overflow detection is now done in the control logic.
//   it gets included with this V in the datapath (exec.v)
	wire V = (carry_32 ^ carry_31)
		| tagged_ovf;


	wire [3:0] alu_cc = {N,Z,V,C};
endmodule


/*
	Malucc module - this module called from Mexec.
	it instantiates Malu and Mccgen above.
 */


module alu34 (big_alu_out, ccN, ccZ, ccV, ccC,
                Ain, Bin,
                carry_in, alu_ADD, alu_AND, alu_XNOR,
                alu_sub, tagged_ovf,
		// random junk
		alu_ADDN, c2, c2N, Ain_d);
 
output[33:0] big_alu_out;
output ccN;
output ccZ;
output ccV;
output ccC;
input [33:0] Ain;
input [33:0] Bin;
input carry_in;
input alu_ADD;
input alu_AND;
input alu_XNOR;
input alu_sub;
input tagged_ovf;
input alu_ADDN, c2, c2N;
output [31:0] Ain_d;

        wire [1:0] alu_s1_high = Ain[33:32];
        wire [1:0] ext_bits = Bin[33:32];

	wire [31:0] Ain_d = Ain[31:0];
                
// synopsys translate_off
        wire carry_32, carry_31;
// synopsys translate_on
 
//      Malu alu (alu_out, carry_32, carry_31,
//              alu_s1sm, alu_s2im, carry_in,
//              alu_ADD, alu_AND, alu_XNOR);
 
        wire [31:0] alu_out;
        Malu alu (alu_out, carry_32, carry_31,
                Ain[31:0], Bin[31:0], carry_in,
                alu_ADD, alu_AND, alu_XNOR);

        wire carry_34;
        wire [1:0] high_2_almost;
        assign {carry_34, high_2_almost} = alu_s1_high + ext_bits + carry_32;

        wire [1:0] high_2 =
                // synopsys translate_off
                (alu_ADD===1'bx) ? 'bx :
                // synopsys translate_on
                alu_ADD ? high_2_almost : 2'bx;

        wire [33:0] big_alu_out = {high_2, alu_out};


// CC GENERATION

        wire [3:0] alu_cc_next; // New CC's based on ALU output

        Mccgen ccgen (alu_cc_next, 
                alu_out, carry_32, carry_31,
                alu_sub, tagged_ovf
        );

        wire ccN = alu_cc_next[3];
        wire ccZ = alu_cc_next[2];
        wire ccV = alu_cc_next[1];
	wire ccC = alu_cc_next[0];
 
endmodule