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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)carry51.v
***
****************************************************************************
****************************************************************************/

//  @(#)carry51.v	1.3  5/28/92
//
// **************************************************************
//  carry51 -- 2-pass generation of carry into bit 51.
// **************************************************************


module carry51(c51, sum, carry, passX1, fpm_clk);

    output c51;

    input [27:0] sum;
    input [27:1] carry;
    input passX1;
    input fpm_clk;


    wire c28, c28_term;

    wire [27:0] carry_bus = (carry[27:1] << 1) ;
    wire [28:0] result ;
    adder29 carryadd (.z(result[28:0]), .x(sum[27:0]), .y(carry_bus[27:0]),
			.CarryIn(c28_term) );

    assign c28_term = c28 & ~passX1;		// clear during passX1

    ME_FD1 carry28Reg (.q(c28),			// c28 is valid during passX2
		       .d(result[28]),
		       .cp(fpm_clk)
		       );

				// we want the carry into bit 23, so use
				// the following property:
				// c51 = (result[23])          ^ a[23] ^ b[23]
				// c51 = (c23 ^ a[23] ^ b[23]) ^ a[23] ^ b[23]
				// c51 = c23

    wire c51_in = result[23] ^ sum[23] ^ carry[23] ;

    ME_FD1 carry51Reg (.q(c51),			// c51 is valid during passX3
		       .d(c51_in),
		       .cp(fpm_clk)
		       );

endmodule