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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)ccdisp.v
***
***
****************************************************************************
****************************************************************************/
// @(#)ccdisp.v 1.8 3/16/93
module Mccdisp
() ;
`define STDOUT 1
`define LOGDCCCYCLES 10
`define DCCCYCLES (1<<`LOGDCCCYCLES)
`define LOGDCCBYTES 10
`define DCCBYTES (1<<`LOGDCCBYTES)
`define DCCVECSIZE (`DCCCYCLES*`DCCBYTES)
// Huge array for holding history samples
reg [7:0] dccvec
[0:(`DCCVECSIZE-1)] ;
reg dccpar
[0:(`DCCVECSIZE-1)] ;
// Cycle at which sampling starts
integer start_cyc
;
// Used for cycles portion of index into dccvec
wire [(`LOGDCCCYCLES-1):0] cidx
= Mclocks.sample_count[(`LOGDCCCYCLES-1):0] ;
// Used for bits portion of index into dccvec
reg [(`LOGDCCBYTES-1):0] bidx
;
// Parameters passed to dcc display loops (global variables)
reg [31:0]
dcc_loopnum
,
dcc_labellen
; // One less than the width of the label field
integer
ccdn
, // Number of cycles to be displayed
from
, to
, // Range of cycles to be displayed
h1
, h2
; // Range of cycles for which samples exist
// When set, samples have been loaded from VCD dump files, not
// from simulation.
reg vcd
;
// Range of cycles loaded from VCD dump
integer vcd_start
, vcd_end
;
// For random functions in vfront.func
integer i
, j
;
// Some event signals used by the dcc display
event dccsig, dccend ;
// Display enough cycles to fill this wide a line
integer line_width
; initial line_width
= 80 ;
// Display variable values for previous n cycles
task ccdisp ;
input relative ; // 1 -> relative to current sample_count, 0 -> abs
input [31:0] x ; // cycle (abs), or offset (rel)
input [31:0] n ;
input [31:0] loopnum ; // vfront loop number of desired display
input [31:0] labellen ; // length of label field
input dcc_scope ; // enable scope display
integer i, j ;
begin
// Test if sample definitions have been given
if (^((vcd===1'b1) ? vcd_start : start_cyc) === 1'bx)
$display("dcc: sampling not initialized") ;
else begin
// Compute number of columns to display
if (n==0) n = (line_width-labellen-2)/3 ;
if (vcd===1'b1) begin
h1 = vcd_start ;
h2 = vcd_end ;
end
else begin
h2 = Mclocks.sample_count ;
h1 = h2 - `DCCCYCLES + 1 ;
if (h1 < start_cyc) h1 = start_cyc ;
end
to = relative ? (h2 - x) : x ;
from = to - n + 1 ;
if (to > h2) to = h2 ;
if (from < h1) from = h1 ;
ccdn = to - from + 1 ;
if ((to < h1) | (from > h2)) ccdn = 0 ;
// Trigger interactively-defined display.
// loopnum identifies which display will trigger.
dcc_loopnum = loopnum ;
dcc_labellen = labellen ;
->dccsig ;
// Wait for it to finish
@dccend ;
end
end
endtask
// Print a header
task header ;
begin
if (ccdn > 0)
$display("(%s %0d through %0d)",
(Mclocks.sample_count==Mclocks.cycle_count)
? "cycles" : "samples",
from, to) ;
end
endtask
// Print a row of hex numbers from dccvec
task hex ;
input [(`LOGDCCBYTES-1):0] bidx ;
input [31:0] labellen ;
reg [(`LOGDCCCYCLES-1):0] cidx ;
reg [7:0] byte ;
begin
pspaces(dcc_labellen-labellen) ;
cidx = from ;
repeat(ccdn) begin
byte = dccvec[{cidx,bidx}] ;
$write(" %h", byte) ;
cidx=(cidx+1);
end
$display("");
end
endtask
// Print a row of 2-char ascii strings from dccvec
task str ;
input [(`LOGDCCBYTES-1):0] bidx ;
input [31:0] labellen ;
reg [(`LOGDCCCYCLES-1):0] cidx ;
reg [7:0] lchar, rchar ;
reg [(`LOGDCCBYTES-1):0] bidx1 ;
begin
pspaces(dcc_labellen-labellen) ;
cidx = from ;
bidx1 = bidx+1 ;
repeat(ccdn) begin
lchar = dccvec[{cidx,bidx1}] ;
rchar = dccvec[{cidx,bidx}] ;
// Convert unknown characters to '?',
// convert non-printing characters to spaces.
if (^lchar===1'bx) lchar = "?" ;
else if (lchar < " ") lchar = " " ;
if (^rchar===1'bx) rchar = "?" ;
else if (rchar < " ") rchar = " " ;
$write(" %c%c", lchar, rchar) ;
cidx=(cidx+1);
end
$display("");
end
endtask
// Print a row of binary numbers from dccvec
task bin ;
input [(`LOGDCCBYTES-1):0] bidx ;
input [2:0] bitnum ;
input [31:0] labellen ;
reg [(`LOGDCCCYCLES-1):0] cidx ;
reg [8:0] byte ;
reg bit ;
begin
pspaces(dcc_labellen-labellen) ;
cidx=from ;
repeat(ccdn) begin
byte = dccvec[{cidx,bidx}] ;
bit = byte[bitnum] ;
if (bit === 1'b0)
$write(" . ") ;
else if (bit === 1'b1)
$write(" ==") ;
else $write(" %b ",bit) ;
cidx= cidx+1 ;
end
$display("");
end
endtask
// Print a row of binary numbers from dccvec, showing clock transitions
task clk ;
input [(`LOGDCCBYTES-1):0] bidx ;
input [2:0] bitnum ;
input [31:0] labellen ;
reg [(`LOGDCCCYCLES-1):0] cidx ;
reg [8:0] byte ;
reg bit ;
begin
pspaces(dcc_labellen-labellen) ;
cidx=from ;
repeat(ccdn) begin
byte = dccvec[{cidx,bidx}] ;
bit = byte[bitnum] ;
if (bit === 1'b0)
$write("--_") ;
else if (bit === 1'b1)
$write("-==") ;
else $write(" %b ",bit) ;
cidx= cidx+1 ;
end
$display("");
end
endtask
// Print a row of binary numbers from dccvec
task nclk ;
input [(`LOGDCCBYTES-1):0] bidx ;
input [2:0] bitnum ;
input [31:0] labellen ;
reg [(`LOGDCCCYCLES-1):0] cidx ;
reg [8:0] byte ;
reg bit ;
begin
pspaces(dcc_labellen-labellen) ;
cidx=from ;
repeat(ccdn) begin
byte = dccvec[{cidx,bidx}] ;
bit = byte[bitnum] ;
if (bit === 1'b0)
$write("_. ") ;
else if (bit === 1'b1)
$write("__-") ;
else $write(" %b ",bit) ;
cidx= cidx+1 ;
end
$display("");
end
endtask
// Print a row of cycle numbers (low-order two decimal digits)
task cycles ;
input [(`LOGDCCBYTES-1):0] bidx ; // (not used)
input [31:0] labellen ;
reg [31:0] i ;
begin
pspaces(dcc_labellen-labellen) ;
i=from ;
repeat(ccdn) begin
$write(" %c%c", 'h30+(i%100)/10,'h30+(i%10) );
i = i+1 ;
end
$display("");
end
endtask
task pspaces ;
input [31:0] n ;
repeat (n) $write(" ");
endtask
// Support for vector files
// Number of vector files allowed, minus 1
`define MAXVEC 29
// This array holds the MCDs for the vector files
integer vec_mcd
[0:31] ;
initial for (i=0;i<32;i=i+1) vec_mcd[i] = 0 ;
// This holds the OR of all the vec_mcd entries (for printing comments
// to all the vector files).
wire [31:0] allvec_mcd
=
vec_mcd[0] | vec_mcd[1] | vec_mcd[2] | vec_mcd[3] |
vec_mcd[4] | vec_mcd[5] | vec_mcd[6] | vec_mcd[7] |
vec_mcd[8] | vec_mcd[9] | vec_mcd[10] | vec_mcd[11] |
vec_mcd[12] | vec_mcd[13] | vec_mcd[14] | vec_mcd[15] |
vec_mcd[16] | vec_mcd[17] | vec_mcd[18] | vec_mcd[19] |
vec_mcd[20] | vec_mcd[21] | vec_mcd[22] | vec_mcd[23] |
vec_mcd[24] | vec_mcd[25] | vec_mcd[26] | vec_mcd[27] |
vec_mcd[28] | vec_mcd[29] | vec_mcd[30] | vec_mcd[31]
;
// For printing to vector files and tto.
wire [31:0] allvec_tto_mcd
= allvec_mcd | 1 ;
// This array records the highest subloop number of each chain.
integer vec_max_subloop
[0:`MAXVEC] ;
// This array holds the current subloop number for each vector file
// while sampling is taking place. The subloops trigger on changes
// to these values.
integer vec_subloop
[0:`MAXVEC] ;
// Another one for the subloops which open the vector files and
// print <signal> description lines.
integer vec_hdr_subloop
[0:`MAXVEC] ;
endmodule
This page: |
Created: | Thu Aug 19 12:03:29 1999 |
| From: |
../../../sparc_v8/env/rtl/ccdisp.v
|