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// @(#)ctl_unit.v 1.22 2/5/93
//
// **************************************************************
// High-level verilog model of FPC control logic
//
// This module defines interface signals and instantiates the
// following modules:
// fhold_ctl, qcore_ctl, depend_ctl, rfrw_ctl, stat_ctl
//
// **************************************************************
module fpc_ctl
(ss_clock, ss_reset, ext_valid_decode, fold_annul_e, ext_hold,
ext_flush, ext_fxack, FpBusyPhi2, fpm_inx, fpm_unfin, fpstat,
fsr_data_in, ir_d, ir_rd_e, ir_rs1_e, ir_rs2_e,
rs1_dbl_issue, fq_rd_used, fq_rs1_dbl, fq_rs1_used,
fq_rs1_0, fq_rs2_0, opf5_q0, fq_ir_0, fq_ir_1, fq_ir_2,
fprf_ra1, fprf_ra2,
ext_fhold, ext_fccv, ext_fexc, fhold_d1, fhold_fqfull_d1,
fpm_start, fpp_fop, fpp_ld, fpp_reset, fq_update,
fload_wait_w, fq_ld_nval, fq_src_sel, fprf_hold_din, fprf_we,
fprf_algn1, fprf_algn2, fprf_byp1, fprf_byp2, fprf_byp3,
fprf_wa, rfin_select, res_select,
fpstmux_sel_e, fsr_out, ss_scan_mode);
input ss_clock
, // FPU clock
ss_reset
, // FPU reset
ext_valid_decode
, // valid instr in decode
fold_annul_e
, // inst in E is annuled
ext_hold
, // IU pipeline held (frozen) from mhold, etc.
ext_flush
, // FPU flush (IU trap)
ext_fxack
, // IU fp_exception acknowledge
FpBusyPhi2
, // FPP busy signal
fpm_inx
, // mul inexact signal
fpm_unfin
; // mul unfinished signal
input [7:0] fpstat
; // Meiko FPP result status bus
input [18:0] fsr_data_in
; // input data (from Data-cache) for the FSR
// fsr_data_in={dc[31:30], dc[27:23], dc[11:0]}
input [31:0] ir_d
; // output of decode instruction register
input [ 4:0] ir_rd_e
, // E-stage instr. reg. field outputs
ir_rs1_e
,
ir_rs2_e
;
input rs1_dbl_issue
; // operand size of FPop being issued
input [ 2:0] fq_rd_used
, // indicates whether or not rd is used
fq_rs1_dbl
, // size of rs1,rs2
fq_rs1_used
; // indicates whether rs1 is used
input fq_rs1_0
, // low bit of rs1 reg field
fq_rs2_0
, // low bit of rs2 reg field
opf5_q0
; // opf[5] of fq0
input [15:0] fq_ir_0
, // output of FQ instruction registers
fq_ir_1
,
fq_ir_2
;
input [ 3:0] fprf_ra1
, // Read address for reg file port 1
fprf_ra2
; // Read address for reg file port 2
input ss_scan_mode
;
output ext_fhold
, // FHOLD signal causes IU to interlock
ext_fccv
, // FP condition codes valid
ext_fexc
, // FP exception signal
fhold_d1
, // delayed ext_fhold used by perf counter
fhold_fqfull_d1
, // delayed fq_full used by perf counter
fpm_start
, // start signal for the multiplier
fpp_fop
, // FpOp for Meiko FPP (start instruction)
fpp_ld
, // FpLd for Meiko FPP (load operands)
fpp_reset
, // reset signal for Meiko FPP
fq_update
, // update fifo for writeback or stdfq
fload_wait_w
; // FPop is currently executing, and may trap
output [2:0] fq_ld_nval
; // FQ load controls, not validated
output [1:0] fq_src_sel
; // FQ instr mux selects
output [1:0] fprf_hold_din
, // FP reg file data in register load control
fprf_we
, // FP reg file write enable controls
fprf_algn1
, // FP reg file port 1 alignment controls
fprf_algn2
; // FP reg file port 2 alignment controls
output [5:0] fprf_byp1
, // FP reg file port 1 internal bypass controls
fprf_byp2
, // FP reg file port 2 internal bypass controls
fprf_byp3
; // FP reg file port 3 internal bypass controls
output [3:0] fprf_wa
; // FP reg file write address
output rfin_select
; // data in source select (D-cache or FPU)
output [1:0] res_select
; // controls Meiko/Mul result select (sgl/dbl)
output [2:0] fpstmux_sel_e
; // FPU store data mux controls
output [22:0] fsr_out
; // FPU status register output (non-constant bits)
wire fpdone
, notrap_writeback
, exemode
, exemode_two
;
wire dir_finst_nostore
, fpop_e
, rs1_dbl_e
, rs1_used_e
, rd_dbl_e
, dir_fop_nval
;
wire dir_fload
, dir_fload_nval
;
wire dir_fstore
, dir_fstore_nval
, mul_fpop_d
, stdfq_e
, stdfq_w
, stdfq_r_noexc
;
wire qne
, qne_fhold
, fq_empty_next
, fq_full_next
, fq_full
;
wire fq_started_0
, fq_type_0
;
wire fcmp_q1q2
, fcmp_q0
, funimp_in_q
;
wire writeback_q0
, wbq0_fhold
, fq_update, unfin_fsmuld
;
wire fsr_ld_nh
, ldst_depend
;
wire fstore_w
, fload_w
, ldf_w
, fload_r
;
wire [2:0] fq_qne
, fq_rd_dbl
;
wire [1:0] op3_w
;
wire [3:0] ls_e
, ls_r
;
wire [4:0] wir_rd
;
// FHOLD_CTL module instance
fhold_ctl fhold1 (ss_clock, ss_reset, ext_flush, ext_hold, ext_valid_decode,
fold_annul_e, exemode, qne_fhold,
fq_full_next, fq_full, fcmp_q0, fcmp_q1q2, funimp_in_q,
writeback_q0, wbq0_fhold, fq_qne[2:0],
ir_d[31:0], ir_rd_e[4:0],
fq_rd_dbl[2:0], fq_rd_used[2:0], fq_rs1_dbl[2:0],
fq_rs1_used[2:0],
fq_ir_0[15:0], fq_ir_1[15:0], fq_ir_2[15:0],
fpop_e, rs1_dbl_e, rs1_used_e, rd_dbl_e, unimpl_fpop_e
,
dir_fstore, fstore_w, dir_finst_nostore, mul_fpop_d,
stdfq_e, stdfq_w, stdfq_r_noexc, ext_fhold, ext_fccv,
fhold_d1, fhold_fqfull_d1, fload_w, ldf_w, op3_w, fload_r,
wir_rd[4:0], ss_scan_mode);
// QCORE_CTL module instance
qcore_ctl qctl1(ss_clock, ss_reset, ext_flush, ext_hold, FpBusyPhi2, fpm_unfin,
fpop_e, rs1_dbl_e, rs1_used_e, rd_dbl_e, unimpl_fpop_e,
mul_fpop_d, notrap_writeback, exemode, exemode_two,
stdfq_r_noexc, opf5_q0, ir_rs1_e[4:0], ir_rs2_e[4:0],
fq_ir_0[15:0], fq_ir_1[15:0],
fq_ir_2[15:0], fq_rd_used[2:0], fq_rs1_used[2:0],
fq_rs1_dbl[2:0],
fq_qne[2:0], fq_ld_nval[2:0], fq_rd_dbl[2:0], fq_src_sel[1:0],
fpm_start, fpp_fop, fpp_ld, fpp_reset, qne, qne_r
, qne_fhold,
fq_empty_next, fq_full_next, fq_full, fq_started_0,
fq_type_0, fcmp_q1q2, fcmp_q0, funimp_in_q, done_q0
,
writeback_q0, wbq0_fhold, fq_update, unfin_fsmuld,
fload_wait_w, res_select[1:0], ss_scan_mode);
// RFRW_CTL module instance
rfrw_ctl rfrwctl1(ss_clock, ss_reset, ext_hold, ext_flush,
fload_w, ldf_w, dir_fstore,
fprf_ra1[3:0], fprf_ra2[3:0], ir_d[20:19], op3_w[1:0],
ir_d[29:25], ir_rd_e[4:0],
wir_rd[4:0], fq_ir_0[15:11],
rs1_dbl_issue,
fq_rd_dbl[0], fq_rs1_0, fq_rs2_0, fcmp_q0,
notrap_writeback, exemode,
fsr_ld_nh, rfin_select,
fpstmux_sel_e[2:0], fprf_hold_din[1:0], fprf_we[1:0],
fprf_algn1[1:0], fprf_algn2[1:0],
fprf_byp1[5:0], fprf_byp2[5:0], fprf_byp3[5:0],
fprf_wa[3:0],
ss_scan_mode);
// STAT_CTL module instance
stat_ctl statctl1(ss_clock, ss_reset, fold_annul_e, ext_flush, fpm_inx,
fpstat, fsr_data_in, fq_qne[0], fq_empty_next, qne,
qne_r, fq_started_0, fq_type_0, fcmp_q0, done_q0,
writeback_q0, unfin_fsmuld, fsr_ld_nh,
ext_hold, ext_fxack, fstore_w, stdfq_e, stdfq_w,
stdfq_r_noexc,
dir_finst_nostore, fsr_out, notrap_writeback, ext_fexc,
exemode, exemode_two, ss_scan_mode);
endmodule
This page: |
Created: | Thu Aug 19 12:02:33 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_fpc/rtl/ctl_unit.v
|