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//  @(#)fp_fpc.v	1.16  2/22/93
//
// **************************************************************
//  High-level verilog model of FPC control logic and registers.
//
// This module defines interface signals and instantiates the
// following modules:
// 	fpc_ctl, fp_qst
//
// **************************************************************


module fp_fpc  (ss_clock, ss_reset, ext_valid_decode, fold_annul_e,
		ext_flush, ext_hold, ext_fxack, hld_dirreg, FpBusyPhi2,
		fpm_inx, fpm_unfin,
		fpstat, fsr_data_in, inst_for_int, iu_epc, fprf_dout3,
		fp_dout_e, FpInst, fpm_inst, RoundingMode, ext_fcc, ext_fhold,
		fpm_start, fpp_fop, fpp_ld, fpp_reset, ext_fexc,
		fhold_d1, fhold_fqfull_d1,
		res_select, rfin_select, fprf_wa, fprf_ra1, fprf_ra2, fprf_ra3,
		fprf_hold_din, fprf_we, fprf_byp1, fprf_byp2, fprf_byp3,
		fprf_algn1, fprf_algn2, ext_fccv, fload_wait_w,
		ss_scan_mode, fp_fpc_scan_in, fp_fpc_scan_out);


input	ss_clock,		// FPU clock
	ss_reset,		// FPU reset
	ext_valid_decode,	// valid instr in decode
	fold_annul_e,		// inst in E is annuled
	ext_flush;		// FPU flush (IU trap)

input [2:0] ext_hold;		// IU pipeline held (frozen) from mhold, etc.

input	ext_fxack,		// FPU exception acknowledge
	hld_dirreg,		// inverted load signal for decode inst reg.
	FpBusyPhi2,		// Meiko FPP busy signal
	fpm_inx,		// MUL inexact result flag
	fpm_unfin;		// MUL unfinished flag

input [7:0] fpstat;		// Meiko status bus
input [18:0] fsr_data_in;	// input data (from Data-cache) for the FSR
				// fsr_data_in={dc[31:30], dc[27:23], dc[11:0]}
input [31:0] inst_for_int;	// Input to D-stage instruction register
input [31:2] iu_epc;		// tap from IU E-stage pc (30-bits)
input [63:0] fprf_dout3;	// operand 1 bus into FPU

input	ss_scan_mode,
	fp_fpc_scan_in;


output [63:0] fp_dout_e;	// output data bus from FPU into the IU
output [9:0] FpInst;		// instruction bus for Meiko core
output [1:0] fpm_inst;		// multiplier instruction (size)
output [1:0] RoundingMode;	// fsr[31:30]
output [1:0] ext_fcc;		// FPU condition codes
output [1:0] res_select;	// controls Meiko/Mul result select (sgl/dbl)
output [3:0] fprf_wa,		// Write address for the reg file (MSB)
	     fprf_ra1,		// Read address for reg file port 1
	     fprf_ra2,		// Read address for reg file port 2
	     fprf_ra3;		// Read address for reg file port 3
output [5:0] fprf_byp1,		// port 1 internal bypass control
	     fprf_byp2,		// port 2 internal bypass control
	     fprf_byp3;		// port 3 internal bypass control
output [1:0] fprf_algn1,	// single-double alignment controls
	     fprf_algn2;
output [1:0] fprf_hold_din ;	// hold control for fprf input data register
output [1:0] fprf_we ;		// fprf write enable controls
output	ext_fhold,		// FHOLD signal causes IU to interlock
	fpm_start,		// MUL start signal
	fpp_fop,		// FP instr. queue load enb (W-cycle)
	fpp_ld,			// FpLd for FPP (read operands)
	fpp_reset,		// reset signal for FPP
	ext_fexc,		// FP exception signal
	fhold_d1,		// delayed ext_fhold used by perf counter
	fhold_fqfull_d1,	// delayed fq_full used by perf counter
	rfin_select,		// reg. file data in source select
	ext_fccv,		// FP condition codes valid
	fload_wait_w,		// FPop is currently executing, and may trap
	fp_fpc_scan_out;	// scan data output


wire [2:0] fpstmux_sel_e;	// fp_dout_e mux selects
wire [22:0] fsr_out;		// FSR non-constant output bits
wire [31:0] ir_d ;		// output of decode instruction register
wire [ 4:0] ir_rd_e,		// E-stage instr. reg. field outputs
	    ir_rs1_e,
	    ir_rs2_e ;
wire rs1_dbl_issue, fq_rs1_0, fq_rs2_0, opf5_q0 ;
wire [2:0] fq_rd_used, fq_rs1_dbl, fq_rs1_used ;
wire [15:0] fq_ir_0,		// FQ entries
	    fq_ir_1,
	    fq_ir_2 ;
wire [2:0] fq_ld_nval ;
wire [1:0] fq_src_sel ;
wire fq_update ;

assign RoundingMode = fsr_out[22:21];
assign ext_fcc = fsr_out[11:10] ;

assign fprf_ra3[3:0] = ir_d[29:26] ;		// ir_rd_d[4:1]


	// FPC control logic
fpc_ctl fpc (ss_clock, ss_reset, ext_valid_decode, fold_annul_e, ext_hold[0],
		ext_flush, ext_fxack, FpBusyPhi2, fpm_inx, fpm_unfin,
		fpstat[7:0], fsr_data_in[18:0], ir_d[31:0], ir_rd_e[4:0],
		ir_rs1_e[4:0], ir_rs2_e[4:0], rs1_dbl_issue,
		fq_rd_used[2:0], fq_rs1_dbl[2:0], fq_rs1_used[2:0],
		fq_rs1_0, fq_rs2_0, opf5_q0, fq_ir_0[15:0],
		fq_ir_1[15:0], fq_ir_2[15:0], fprf_ra1[3:0], fprf_ra2[3:0],
		ext_fhold, ext_fccv, ext_fexc, fhold_d1, fhold_fqfull_d1,
		fpm_start, fpp_fop, fpp_ld,
		fpp_reset, fq_update, fload_wait_w, fq_ld_nval[2:0],
		fq_src_sel[1:0], fprf_hold_din[1:0], fprf_we[1:0],
		fprf_algn1[1:0], fprf_algn2[1:0], fprf_byp1[5:0],
		fprf_byp2[5:0], fprf_byp3[5:0], fprf_wa[3:0],
		rfin_select, res_select[1:0],
		fpstmux_sel_e[2:0], fsr_out[22:0], ss_scan_mode);


	// FPC registers (used to be the fp_qst datapath)
fp_qst fpqst (ss_clock, inst_for_int[31:0], iu_epc[31:2], fsr_out[22:0],
		fprf_dout3[63:0], fq_ld_nval[2:0], fq_src_sel[1:0],
		fpstmux_sel_e[2:0], hld_dirreg, fq_update, ext_hold[2],
		ext_flush,
		ir_d[31:0], ir_rd_e[4:0], ir_rs1_e[4:0], ir_rs2_e[4:0],
		rs1_dbl_issue, fq_rd_used[2:0],
		fq_rs1_dbl[2:0], fq_rs1_used[2:0], fq_rs1_0, fq_rs2_0, opf5_q0,
		fq_ir_0[15:0], fq_ir_1[15:0], fq_ir_2[15:0],
		fprf_ra1[3:0], fprf_ra2[3:0], FpInst[9:0], fpm_inst[1:0],
		fp_dout_e[63:0]);

endmodule